1 /* 2 * Copyright (c) 2024 Nordic Semiconductor ASA 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @brief Header containing SPI device specific declarations for the 9 * Zephyr OS layer of the Wi-Fi driver. 10 */ 11 12 #ifndef __SPI_NOR_H__ 13 #define __SPI_NOR_H__ 14 15 #include <zephyr/sys/util.h> 16 17 #define SPI_NOR_MAX_ID_LEN 3 18 19 /* Status register bits */ 20 #define SPI_NOR_WIP_BIT BIT(0) /* Write in progress */ 21 #define SPI_NOR_WEL_BIT BIT(1) /* Write enable latch */ 22 23 /* Flash opcodes */ 24 #define SPI_NOR_CMD_WRSR 0x01 /* Write status register */ 25 #define SPI_NOR_CMD_RDSR 0x05 /* Read status register */ 26 #define SPI_NOR_CMD_READ 0x03 /* Read data */ 27 #define SPI_NOR_CMD_WREN 0x06 /* Write enable */ 28 #define SPI_NOR_CMD_WRDI 0x04 /* Write disable */ 29 #define SPI_NOR_CMD_PP 0x02 /* Page program */ 30 #define SPI_NOR_CMD_SE 0x20 /* Sector erase */ 31 #define SPI_NOR_CMD_BE_32K 0x52 /* Block erase 32KB */ 32 #define SPI_NOR_CMD_BE 0xD8 /* Block erase */ 33 #define SPI_NOR_CMD_CE 0xC7 /* Chip erase */ 34 #define SPI_NOR_CMD_RDID 0x9F /* Read JEDEC ID */ 35 #define SPI_NOR_CMD_ULBPR 0x98 /* Global Block Protection Unlock */ 36 #define SPI_NOR_CMD_4BA 0xB7 /* Enter 4-Byte Address Mode */ 37 #define SPI_NOR_CMD_DPD 0xB9 /* Deep Power Down */ 38 #define SPI_NOR_CMD_RDPD 0xAB /* Release from Deep Power Down */ 39 40 /* Page, sector, and block size are standard, not configurable. */ 41 #define SPI_NOR_PAGE_SIZE 0x0100U 42 #define SPI_NOR_SECTOR_SIZE 0x1000U 43 #define SPI_NOR_BLOCK_SIZE 0x10000U 44 45 /* Test whether offset is aligned to a given number of bits. */ 46 #define SPI_NOR_IS_ALIGNED(_ofs, _bits) (((_ofs)&BIT_MASK(_bits)) == 0) 47 #define SPI_NOR_IS_SECTOR_ALIGNED(_ofs) SPI_NOR_IS_ALIGNED(_ofs, 12) 48 49 #endif /*__SPI_NOR_H__*/ 50
