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/Zephyr-Core-3.5.0/dts/arm/cypress/
Dpsoc6_cm0.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
13 compatible = "arm,cortex-m0+";
16 /delete-node/ cpu@1;
21 /* see cypress,psoc6-int-mux.yaml */
22 compatible = "cypress,psoc6-intmux";
26 #address-cells = <1>;
27 #size-cells = <1>;
29 intmux_ch0: interrupt-controller@0 {
30 compatible = "cypress,psoc6-intmux-ch";
[all …]
/Zephyr-Core-3.5.0/dts/riscv/
Dvirt.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 * qemu-system-riscv32 -machine virt,dumpdtb=virt.dtb -smp 8 -m 256
13 /dts-v1/;
16 #address-cells = < 0x01 >;
17 #size-cells = < 0x01 >;
18 compatible = "riscv-virtio";
19 model = "riscv-virtio,qemu";
22 bank-width = < 0x04 >;
24 compatible = "cfi-flash";
29 interrupt-parent = < &plic >;
[all …]
/Zephyr-Core-3.5.0/dts/riscv/openisa/
Drv32m1.dtsi3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/interrupt-controller/openisa-intmux.h>
7 #include <zephyr/dt-bindings/gpio/gpio.h>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/pwm/pwm.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
17 zephyr,flash-controller = &ftfe;
21 #address-cells = <1>;
22 #size-cells = <0>;
[all …]
/Zephyr-Core-3.5.0/dts/riscv/microchip/
Dmpfs-icicle.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
18 clock-frequency = <0>;
23 hlic0: interrupt-controller {
24 compatible = "riscv,cpu-intc";
25 #address-cells = <0>;
[all …]
Dmicrochip-miv.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #address-cells = <1>;
9 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 clock-frequency = <0>;
20 hlic: interrupt-controller {
21 compatible = "riscv,cpu-intc";
22 #address-cells = <0>;
23 #interrupt-cells = <1>;
[all …]
/Zephyr-Core-3.5.0/scripts/dts/python-devicetree/tests/
Dtest.dts4 * SPDX-License-Identifier: BSD-3-Clause
9 /dts-v1/;
16 interrupt-parent-test {
18 compatible = "interrupt-three-cell";
19 #interrupt-cells = <3>;
20 interrupt-controller;
24 interrupt-names = "foo", "bar";
25 interrupt-parent = <&{/interrupt-parent-test/controller}>;
28 interrupts-extended-test {
29 controller-0 {
[all …]
/Zephyr-Core-3.5.0/dts/riscv/sifive/
Driscv64-fu740.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
13 compatible = "sifive,FU740-C000", "fu740-dev", "sifive-dev";
17 coreclk: core-clk {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <DT_FREQ_M(1000)>;
23 pclk: p-clk {
[all …]
Driscv64-fu540.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "sifive,FU540-C000", "fu540-dev", "sifive-dev";
17 coreclk: core-clk {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <DT_FREQ_M(1000)>;
23 tlclk: tl-clk {
[all …]
Driscv32-fe310.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <zephyr/dt-bindings/gpio/gpio.h>
4 #include <zephyr/dt-bindings/pwm/pwm.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 compatible = "sifive,FE310G-0002-Z0-dev", "fe310-dev", "sifive-dev";
11 model = "SiFive,FE310G-0002-Z0";
13 coreclk: core-clk {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
[all …]
/Zephyr-Core-3.5.0/dts/riscv/andes/
Dandes_v5_ae350.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <60000000>;
25 mmu-type = "riscv,sv32";
26 clock-frequency = <60000000>;
[all …]
/Zephyr-Core-3.5.0/dts/arc/synopsys/
Darc_iot.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
24 intc: arcv2-intc {
25 compatible = "snps,arcv2-intc";
26 interrupt-controller;
27 #interrupt-cells = <2>;
31 compatible = "snps,arc-timer";
[all …]
Demsk.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
25 intc: arcv2-intc {
26 compatible = "snps,arcv2-intc";
27 interrupt-controller;
28 #interrupt-cells = <2>;
32 compatible = "snps,arc-timer";
[all …]
Demsdp.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 //#include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
26 intc: arcv2-intc {
27 compatible = "snps,arcv2-intc";
28 interrupt-controller;
29 #interrupt-cells = <2>;
33 compatible = "snps,arc-timer";
[all …]
Darc_hs4xd.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
43 intc: arcv2-intc {
44 compatible = "snps,arcv2-intc";
45 interrupt-controller;
46 #interrupt-cells = <2>;
50 idu_intc: idu-interrupt-controller {
[all …]
Darc_hsdk.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
43 intc: arcv2-intc {
44 compatible = "snps,arcv2-intc";
45 interrupt-controller;
46 #interrupt-cells = <2>;
50 idu_intc: idu-interrupt-controller {
[all …]
/Zephyr-Core-3.5.0/dts/x86/intel/
Delkhart_lake.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,elkhart-lake";
20 d-cache-line-size = <64>;
38 #address-cells = <1>;
39 #interrupt-cells = <3>;
[all …]
Draptor_lake.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/pcie/pcie.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,raptor-lake";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
[all …]
Dalder_lake.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "intel,alder-lake";
21 d-cache-line-size = <64>;
34 #address-cells = <1>;
[all …]
Dintel_ish5.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <dt-bindings/i2c/i2c.h>
13 power-states {
15 compatible = "zephyr,power-state";
16 power-state-name = "runtime-idle";
17 min-residency-us = <500>;
18 substate-id = <1>;
22 compatible = "zephyr,power-state";
23 power-state-name = "suspend-to-idle";
[all …]
Dia32.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
12 #address-cells = <1>;
13 #size-cells = <0>;
18 d-cache-line-size = <64>;
26 #address-cells = <1>;
27 #interrupt-cells = <3>;
29 interrupt-controller;
35 interrupt-controller;
36 #interrupt-cells = <3>;
[all …]
/Zephyr-Core-3.5.0/dts/riscv/lowrisc/
Dopentitan_earlgrey.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #address-cells = <0x01>;
9 #size-cells = <0x01>;
10 compatible = "lowrisc,opentitan-earlgrey";
13 #address-cells = <0x01>;
14 #size-cells = <0x00>;
15 timebase-frequency = <10000000>;
24 hlic: interrupt-controller {
25 #interrupt-cells = <0x01>;
26 interrupt-controller;
[all …]
/Zephyr-Core-3.5.0/dts/riscv/telink/
Dtelink_b91.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/adc/b91-adc.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
20 #address-cells = <1>;
[all …]
/Zephyr-Core-3.5.0/dts/riscv/efinix/
Dsapphire_soc.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
29 clock-frequency = <100000000>;
35 timebase-frequency = <100000000>;
37 hlic: interrupt-controller {
38 compatible = "riscv,cpu-intc";
[all …]
/Zephyr-Core-3.5.0/dts/xtensa/intel/
Dintel_adsp_cavs15.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "cdns,tensilica-xtensa-lx4";
19 i-cache-line-size = <64>;
20 d-cache-line-size = <64>;
25 compatible = "cdns,tensilica-xtensa-lx4";
31 compatible = "mmio-sram";
36 compatible = "mmio-sram";
40 sysclk: system-clock {
[all …]
/Zephyr-Core-3.5.0/tests/drivers/build_all/gpio/
Daltera.overlay4 * SPDX-License-Identifier: Apache-2.0
9 #address-cells = <1>;
10 #size-cells = <1>;
13 #address-cells = <1>;
14 #size-cells = <1>;
15 test_intc: interrupt-controller {
16 compatible = "riscv,cpu-intc";
17 #address-cells = < 0x0 >;
18 #interrupt-cells = < 0x1 >;
19 interrupt-controller;
[all …]

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