1/*
2 * Copyright (c) 2023 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include "skeleton.dtsi"
8#include <dt-bindings/interrupt-controller/intel-ioapic.h>
9#include <dt-bindings/i2c/i2c.h>
10#include <mem.h>
11
12/ {
13	power-states {
14		d0i0: d0i0 {
15			compatible = "zephyr,power-state";
16			power-state-name = "runtime-idle";
17			min-residency-us = <500>;
18			substate-id = <1>;
19		};
20
21		d0i1: d0i1 {
22			compatible = "zephyr,power-state";
23			power-state-name = "suspend-to-idle";
24			min-residency-us = <2000>;
25			substate-id = <2>;
26		};
27
28		d0i2: d0i2 {
29			compatible = "zephyr,power-state";
30			power-state-name = "suspend-to-ram";
31			min-residency-us = <4000>;
32			substate-id = <3>;
33		};
34
35		d0i3: d0i3 {
36			compatible = "zephyr,power-state";
37			power-state-name = "suspend-to-disk";
38			min-residency-us = <3000000>;
39			substate-id = <4>;
40		};
41	};
42
43	cpus {
44		#address-cells = <1>;
45		#size-cells = <0>;
46
47		cpu0: cpu0@0 {
48			device_type = "cpu";
49			compatible = "intel,ish";
50			reg = <0>;
51			cpu-power-states = <&d0i0 &d0i1 &d0i2 &d0i3>;
52		};
53	};
54
55	intc: ioapic@fec00000  {
56		compatible = "intel,ioapic";
57		#address-cells = <1>;
58		#interrupt-cells = <3>;
59		reg = <0xfec00000 0x1000>;
60		interrupt-controller;
61	};
62
63	intc_loapic: loapic@fee00000  {
64		compatible = "intel,loapic";
65		reg = <0xfee00000 0x1000>;
66		interrupt-controller;
67		#interrupt-cells = <3>;
68		#address-cells = <1>;
69	};
70
71	sram: memory@ff200000 {
72		device_type = "memory";
73		compatible = "mmio-sram";
74		reg = <0xff200000 DT_SIZE_K(640)>;
75	};
76
77	aon: memory@ff800000 {
78		device_type = "memory";
79		compatible = "zephyr,memory-region", "mmio-sram";
80		reg = <0xff800000 DT_SIZE_K(8)>;
81		zephyr,memory-region = "AON";
82	};
83
84	soc {
85		#address-cells = <1>;
86		#size-cells = <1>;
87		compatible = "simple-bus";
88		ranges;
89
90		hpet: hpet@4700000{
91			compatible = "intel,hpet";
92			reg = <0x04700000 0x400>;
93			interrupt-parent = <&intc>;
94			interrupts = <14 IRQ_TYPE_FIXED_LEVEL_HIGH 2>;
95			status = "okay";
96		};
97
98		ipmhost: ipm@4100000 {
99			compatible = "intel,sedi-ipm";
100			reg = <0x4100000 0x1000>;
101			peripheral-id = <0>;
102			interrupt-parent = <&intc>;
103			interrupts = <0 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;
104
105			status = "okay";
106		};
107
108		uart0: uart@8100000 {
109			compatible = "intel,sedi-uart";
110			reg = <0x08100000 0x1000>;
111			interrupt-parent = <&intc>;
112			interrupts = <23 IRQ_TYPE_LOWEST_EDGE_RISING 6>;
113			peripheral-id = <0>;
114			current-speed = <115200>;
115			status = "okay";
116		};
117
118		i2c0: i2c@0 {
119			compatible = "intel,sedi-i2c";
120			#address-cells = <1>;
121			#size-cells = <0>;
122			reg = <0x0 0x1000>;
123			peripheral-id = <0>;
124			interrupt-parent = <&intc>;
125			interrupts = <15 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;
126			clock-frequency = <I2C_BITRATE_FAST>;
127			status = "okay";
128		};
129
130		i2c1: i2c@2000 {
131			compatible = "intel,sedi-i2c";
132			#address-cells = <1>;
133			#size-cells = <0>;
134			reg = <0x00002000 0x1000>;
135			peripheral-id = <1>;
136			interrupt-parent = <&intc>;
137			interrupts = <16 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;
138			clock-frequency = <I2C_BITRATE_FAST>;
139			status = "okay";
140		};
141
142		i2c2: i2c@4000 {
143			compatible = "intel,sedi-i2c";
144			#address-cells = <1>;
145			#size-cells = <0>;
146			reg = <0x00004000 0x1000>;
147			peripheral-id = <2>;
148			interrupt-parent = <&intc>;
149			interrupts = <17 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;
150			clock-frequency = <I2C_BITRATE_FAST>;
151			status = "disabled";
152		};
153
154		gpio0: gpio@100000 {
155			compatible = "intel,sedi-gpio";
156			gpio-controller;
157			#gpio-cells = <2>;
158			peripheral-id = <0>;
159			reg = <0x00100000 0x1000>;
160			interrupt-parent = <&intc>;
161			ngpios = <32>;
162			interrupts = <13 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;
163
164			status = "okay";
165		};
166	};
167};
168