1/*
2 * Copyright (c) 2018, Synopsys, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include "skeleton.dtsi"
8
9#include <zephyr/dt-bindings/i2c/i2c.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11
12/ {
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu0: cpu@0 {
18			device_type = "cpu";
19			compatible = "snps,arcem";
20			reg = <0>;
21		};
22	};
23
24	intc: arcv2-intc {
25		compatible = "snps,arcv2-intc";
26		interrupt-controller;
27		#interrupt-cells = <2>;
28	};
29
30	timer0: timer0 {
31		compatible = "snps,arc-timer";
32		interrupts = <16 1>;
33		interrupt-parent = <&intc>;
34	};
35
36	sysconf: system-configuration@f000a000 {
37		compatible = "snps,arc-iot-sysconf";
38		reg = <0xf000a000 0x90>;
39	};
40
41	iccm0: iccm@20000000 {
42		compatible = "arc,iccm";
43		reg = <0x20000000 0x40000>;
44	};
45
46	dccm0: dccm@80000000 {
47		compatible = "arc,dccm";
48		reg = <0x80000000 0x20000>;
49	};
50
51
52	sram: memory@30000000 {
53		compatible = "mmio-sram";
54		reg = <0x30000000 0x20000>;
55	};
56
57	flash0: flash@0 {
58		compatible = "soc-nv-flash";
59		reg = <0x0 0x40000>;
60	};
61
62	sysclk: system-clock {
63		compatible = "fixed-clock";
64		clock-frequency = <144000000>;
65		#clock-cells = <0>;
66	};
67
68	soc {
69		#address-cells = <1>;
70		#size-cells = <1>;
71		compatible = "simple-bus";
72		ranges;
73
74
75		uart0: uart@80014000 {
76			compatible = "ns16550";
77			clock-frequency = <16000000>;
78			reg = <0x80014000 0x100>;
79			io-mapped;
80			interrupts = <86 0>;
81			interrupt-parent = <&intc>;
82			dlf = <0x01>;
83			reg-shift = <2>;
84		};
85
86		uart1: uart@80014100 {
87			compatible = "ns16550";
88			clock-frequency = <16000000>;
89			reg = <0x80014100 0x100>;
90			io-mapped;
91			interrupts = <87 0>;
92			interrupt-parent = <&intc>;
93			reg-shift = <2>;
94			status = "disabled";
95		};
96
97		uart2: uart@80014200 {
98			compatible = "ns16550";
99			clock-frequency = <16000000>;
100			reg = <0x80014200 0x1000>;
101			io-mapped;
102			interrupts = <88 0>;
103			interrupt-parent = <&intc>;
104			reg-shift = <2>;
105			status = "disabled";
106		};
107
108		uart3: uart@80014300 {
109			compatible = "ns16550";
110			clock-frequency = <144000000>;
111			reg = <0x80014300 0x100>;
112			io-mapped;
113			interrupts = <89 0>;
114			interrupt-parent = <&intc>;
115			reg-shift = <2>;
116			status = "disabled";
117		};
118
119		gpio8b0: gpio@80017800 {
120			reg = <0x80017800 0x100>;
121			interrupts = <54 1>;
122			interrupt-parent = <&intc>;
123
124			gpio-controller;
125			#gpio-cells = <2>;
126
127			status = "disabled";
128		};
129
130		gpio8b1: gpio@80017900 {
131			reg = <0x80017900 0x100>;
132			interrupts = <55 1>;
133			interrupt-parent = <&intc>;
134
135			gpio-controller;
136			#gpio-cells = <2>;
137
138			status = "disabled";
139		};
140
141		gpio8b2: gpio@80017a00 {
142			reg = <0x80017a00 0x100>;
143			interrupts = <56 1>;
144			interrupt-parent = <&intc>;
145
146			gpio-controller;
147			#gpio-cells = <2>;
148
149			status = "disabled";
150		};
151
152		gpio8b3: gpio@80017b00 {
153			reg = <0x80017b00 0x100>;
154			interrupts = <57 1>;
155			interrupt-parent = <&intc>;
156
157			gpio-controller;
158			#gpio-cells = <2>;
159
160			status = "disabled";
161		};
162
163		gpio4b0: gpio@80017c00 {
164			reg = <0x80017c00 0x100>;
165			interrupts = <19 1>;
166			interrupt-parent = <&intc>;
167
168			gpio-controller;
169			#gpio-cells = <2>;
170		};
171
172		gpio4b1: gpio@80017d00 {
173			reg = <0x80017d00 0x100>;
174			interrupts = <52 1>;
175			interrupt-parent = <&intc>;
176
177			gpio-controller;
178			#gpio-cells = <2>;
179
180			status = "disabled";
181		};
182
183		gpio4b2: gpio@80017e00 {
184			reg = <0x80017e00 0x100>;
185			interrupts = <53 1>;
186			interrupt-parent = <&intc>;
187
188			gpio-controller;
189			#gpio-cells = <2>;
190
191			status = "disabled";
192		};
193
194
195		i2c0: i2c@80012000 {
196			clock-frequency = <I2C_BITRATE_STANDARD>;
197			#address-cells = <1>;
198			#size-cells = <0>;
199			reg = <0x80012000 0x100>;
200			interrupts = <58 1>, <61 1>, <60 1>, <59 1>;
201			interrupt-names = "error", "stop", "tx", "rx";
202			interrupt-parent = <&intc>;
203
204			status = "disabled";
205		};
206
207		i2c1: i2c@80012100 {
208			clock-frequency = <I2C_BITRATE_STANDARD>;
209			#address-cells = <1>;
210			#size-cells = <0>;
211			reg = <0x80012100 0x100>;
212			interrupts = <62 1>, <65 1>, <64 1>, <63 1>;
213			interrupt-names = "error", "stop", "tx", "rx";
214			interrupt-parent = <&intc>;
215
216			status = "disabled";
217		};
218
219		i2c2: i2c@80012200 {
220			clock-frequency = <I2C_BITRATE_STANDARD>;
221			#address-cells = <1>;
222			#size-cells = <0>;
223			reg = <0x80012200 0x100>;
224			interrupts = <66 1>, <69 1>, <68 1>, <67 1>;
225			interrupt-names = "error", "stop", "tx", "rx";
226			interrupt-parent = <&intc>;
227
228			status = "disabled";
229		};
230
231		spi0: spi@80010000 {
232			compatible = "snps,designware-spi";
233			#address-cells = <1>;
234			#size-cells = <0>;
235			reg = <0x80010000 0x100>;
236			clocks = <&sysclk>;
237			interrupts = <70 2>, <71 2>, <72 2>;
238			interrupt-names = "err-int", "rx-avail", "tx-req";
239			interrupt-parent = <&intc>;
240			status = "disabled";
241		};
242
243		spi1: spi@80010100 {
244			compatible = "snps,designware-spi";
245			#address-cells = <1>;
246			#size-cells = <0>;
247			reg = <0x80010100 0x100>;
248			clocks = <&sysclk>;
249			interrupts = <74 2>, <75 2>, <76 2>;
250			interrupt-names = "err-int", "rx-avail", "tx-req";
251			interrupt-parent = <&intc>;
252			status = "disabled";
253		};
254
255		spi2: spi@80010200 {
256			compatible = "snps,designware-spi";
257			#address-cells = <1>;
258			#size-cells = <0>;
259			reg = <0x80010200 0x100>;
260			clocks = <&sysclk>;
261			interrupts = <78 2>, <79 2>, <80 2>;
262			interrupt-names = "err-int", "rx-avail", "tx-req";
263			interrupt-parent = <&intc>;
264			status = "disabled";
265		};
266
267	};
268};
269