1/*
2 * Copyright (c) 2021 Katsuhiro Suzuki
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/dt-bindings/gpio/gpio.h>
8#include <freq.h>
9
10/ {
11	#address-cells = <2>;
12	#size-cells = <2>;
13	compatible = "sifive,FU740-C000", "fu740-dev", "sifive-dev";
14	model = "sifive,FU740";
15
16	clocks {
17		coreclk: core-clk {
18			#clock-cells = <0>;
19			compatible = "fixed-clock";
20			clock-frequency = <DT_FREQ_M(1000)>;
21		};
22
23		pclk: p-clk {
24			#clock-cells = <0>;
25			compatible = "fixed-clock";
26			clock-frequency = <DT_FREQ_K(125125)>;
27		};
28	};
29
30	cpus {
31		#address-cells = <1>;
32		#size-cells = <0>;
33
34		cpu0: cpu@0 {
35			compatible = "sifive,s7";
36			device_type = "cpu";
37			reg = <0>;
38			riscv,isa = "rv64imac_zicsr_zifencei";
39			status = "okay";
40
41			hlic: interrupt-controller {
42				compatible = "riscv,cpu-intc";
43				#address-cells = <0>;
44				#interrupt-cells = <1>;
45				interrupt-controller;
46			};
47		};
48		cpu1: cpu@1 {
49			compatible = "sifive,u74";
50			device_type = "cpu";
51			mmu-type = "riscv,sv39";
52			reg = <0x1>;
53			riscv,isa = "rv64gc";
54
55			cpu1_intc: interrupt-controller {
56				compatible = "riscv,cpu-intc";
57				#interrupt-cells = <1>;
58				interrupt-controller;
59			};
60		};
61		cpu2: cpu@2 {
62			compatible = "sifive,u74";
63			device_type = "cpu";
64			mmu-type = "riscv,sv39";
65			reg = <0x2>;
66			riscv,isa = "rv64gc";
67
68			cpu2_intc: interrupt-controller {
69				compatible = "riscv,cpu-intc";
70				#interrupt-cells = <1>;
71				interrupt-controller;
72			};
73		};
74		cpu3: cpu@3 {
75			compatible = "sifive,u74";
76			device_type = "cpu";
77			mmu-type = "riscv,sv39";
78			reg = <0x3>;
79			riscv,isa = "rv64gc";
80
81			cpu3_intc: interrupt-controller {
82				compatible = "riscv,cpu-intc";
83				#interrupt-cells = <1>;
84				interrupt-controller;
85			};
86		};
87		cpu4: cpu@4 {
88			compatible = "sifive,u74";
89			device_type = "cpu";
90			mmu-type = "riscv,sv39";
91			reg = <0x4>;
92			riscv,isa = "rv64gc";
93
94			cpu4_intc: interrupt-controller {
95				compatible = "riscv,cpu-intc";
96				#interrupt-cells = <1>;
97				interrupt-controller;
98			};
99		};
100	};
101
102	soc {
103		#address-cells = <2>;
104		#size-cells = <2>;
105		compatible = "simple-bus";
106		ranges;
107
108		modeselect: rom@1000 {
109			compatible = "sifive,modeselect0";
110			reg = <0x0 0x1000 0x0 0x1000>;
111			reg-names = "mem";
112		};
113
114		maskrom: rom@10000 {
115			compatible = "sifive,maskrom0";
116			reg = <0x0 0x10000 0x0 0x8000>;
117			reg-names = "mem";
118		};
119
120		dtim: dtim@1000000 {
121			compatible = "sifive,dtim0";
122			reg = <0x0 0x1000000 0x0 0x2000>;
123			reg-names = "mem";
124		};
125
126		clint: clint@2000000 {
127			compatible = "sifive,clint0";
128			interrupts-extended = <&hlic 3 &hlic 7>;
129			reg = <0x0 0x2000000 0x0 0x10000>;
130		};
131
132		l2lim: l2lim@8000000 {
133			compatible = "sifive,l2lim0";
134			reg = <0x0 0x8000000 0x0 0x200000>;
135			reg-names = "mem";
136		};
137
138
139		plic: interrupt-controller@c000000 {
140			compatible = "sifive,plic-1.0.0";
141			#address-cells = <0>;
142			#interrupt-cells = <2>;
143			interrupt-controller;
144			interrupts-extended = <&hlic 11>;
145			reg = <0x0 0x0c000000 0x0 0x04000000>;
146			riscv,max-priority = <7>;
147			riscv,ndev = <52>;
148		};
149
150		uart0: serial@10010000 {
151			compatible = "sifive,uart0";
152			interrupt-parent = <&plic>;
153			interrupts = <39 1>;
154			reg = <0x0 0x10010000 0x0 0x1000>;
155			reg-names = "control";
156			status = "disabled";
157		};
158
159		uart1: serial@10011000 {
160			compatible = "sifive,uart0";
161			interrupt-parent = <&plic>;
162			interrupts = <40 1>;
163			reg = <0x0 0x10011000 0x0 0x1000>;
164			reg-names = "control";
165			status = "disabled";
166		};
167
168		spi0: spi@10040000 {
169			compatible = "sifive,spi0";
170			interrupt-parent = <&plic>;
171			interrupts = <41 1>;
172			reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>;
173			reg-names = "control", "mem";
174			status = "disabled";
175			#address-cells = <1>;
176			#size-cells = <0>;
177		};
178
179		spi1: spi@10041000 {
180			compatible = "sifive,spi0";
181			interrupt-parent = <&plic>;
182			interrupts = <42 1>;
183			reg = <0x0 0x10041000 0x0 0x1000>;
184			reg-names = "control";
185			status = "disabled";
186			#address-cells = <1>;
187			#size-cells = <0>;
188		};
189
190		spi2: spi@10050000 {
191			compatible = "sifive,spi0";
192			interrupt-parent = <&plic>;
193			interrupts = <43 1>;
194			reg = <0x0 0x10050000 0x0 0x1000>;
195			reg-names = "control";
196			status = "disabled";
197			#address-cells = <1>;
198			#size-cells = <0>;
199		};
200		dmc: dmc@100b0000 {
201			compatible = "sifive,fu740-c000-ddr";
202			reg = <0x0 0x100b0000 0x0 0x0800
203			       0x0 0x100b2000 0x0 0x2000
204			       0x0 0x100b8000 0x0 0x1000>;
205			status = "disabled";
206		};
207	};
208};
209