1/*
2 * Copyright (c) 2017 Intel Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include "skeleton.dtsi"
8#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9
10/ {
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14
15		cpu@0 {
16			device_type = "cpu";
17			compatible = "intel,x86";
18			d-cache-line-size = <64>;
19			reg = <0>;
20		};
21
22	};
23
24	intc: ioapic@fec00000  {
25		compatible = "intel,ioapic";
26		#address-cells = <1>;
27		#interrupt-cells = <3>;
28		reg = <0xfec00000 0x1000>;
29		interrupt-controller;
30	};
31
32	intc_loapic: loapic@fee00000  {
33		compatible = "intel,loapic";
34		reg = <0xfee00000 0x1000>;
35		interrupt-controller;
36		#interrupt-cells = <3>;
37		#address-cells = <1>;
38	};
39
40	dram0: memory@0 {
41		device_type = "memory";
42		reg = <DT_DRAM_BASE DT_DRAM_SIZE>;
43	};
44
45	soc {
46		#address-cells = <1>;
47		#size-cells = <1>;
48		compatible = "simple-bus";
49		ranges;
50
51		uart0: uart@3f8 {
52			compatible = "ns16550";
53			reg = <0x000003f8 0x100>;
54			io-mapped;
55			clock-frequency = <1843200>;
56			interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
57			interrupt-parent = <&intc>;
58			reg-shift = <0>;
59			status = "disabled";
60		};
61
62		uart1: uart@2f8 {
63			compatible = "ns16550";
64			reg = <0x000002f8 0x100>;
65			io-mapped;
66			clock-frequency = <1843200>;
67			interrupts = <3 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
68			interrupt-parent = <&intc>;
69			reg-shift = <0>;
70			status = "disabled";
71		};
72
73		hpet: hpet@fed00000 {
74			compatible = "intel,hpet";
75			reg = <0xfed00000 0x400>;
76			interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
77			interrupt-parent = <&intc>;
78
79			status = "disabled";
80		};
81
82		rtc: counter: rtc@70 {
83			compatible = "motorola,mc146818";
84			reg = <0x70 0x0D 0x71 0x0D>;
85			interrupts = <8 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
86			interrupt-parent = <&intc>;
87			alarms-count = <1>;
88
89			status = "okay";
90		};
91
92	};
93};
94