Lines Matching +full:interrupt +full:- +full:cells

4  * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
11 	#address-cells = <1>;
12 	#size-cells = <1>;
13 	compatible = "sifive,FU540-C000", "fu540-dev", "sifive-dev";
17 		coreclk: core-clk {
18 			#clock-cells = <0>;
19 			compatible = "fixed-clock";
20 			clock-frequency = <DT_FREQ_M(1000)>;
23 		tlclk: tl-clk {
24 			#clock-cells = <0>;
25 			compatible = "fixed-factor-clock";
27 			clock-div = <2>;
32 		#address-cells = <1>;
33 		#size-cells = <0>;
42 			hlic: interrupt-controller {
43 				compatible = "riscv,cpu-intc";
44 				#address-cells = <0>;
45 				#interrupt-cells = <1>;
46 				interrupt-controller;
52 		#address-cells = <1>;
53 		#size-cells = <1>;
54 		compatible = "simple-bus";
60 			reg-names = "mem";
66 			reg-names = "mem";
72 			reg-names = "mem";
78 			reg-names = "mem";
84 			reg-names = "mem";
90 			reg-names = "mem";
96 			reg-names = "mem";
102 			reg-names = "mem";
107 			interrupts-extended = <&hlic 3 &hlic 7>;
114 			reg-names = "mem";
117 		plic: interrupt-controller@c000000 {
118 			compatible = "sifive,plic-1.0.0";
119 			#address-cells = <0>;
120 			#interrupt-cells = <2>;
121 			interrupt-controller;
122 			interrupts-extended = <&hlic 11>;
124 			riscv,max-priority = <7>;
130 			interrupt-parent = <&plic>;
133 			reg-names = "control";
139 			interrupt-parent = <&plic>;
142 			reg-names = "control";
148 			interrupt-parent = <&plic>;
151 			reg-names = "control", "mem";
153 			#address-cells = <1>;
154 			#size-cells = <0>;
159 			interrupt-parent = <&plic>;
162 			reg-names = "control";
164 			#address-cells = <1>;
165 			#size-cells = <0>;
170 			interrupt-parent = <&plic>;
173 			reg-names = "control";
175 			#address-cells = <1>;
176 			#size-cells = <0>;
181 			gpio-controller;
182 			interrupt-parent = <&plic>;
188 			reg-names = "control";
190 			#gpio-cells = <2>;
192 			#address-cells = <1>;
193 			#size-cells = <1>;