Home
last modified time | relevance | path

Searched +full:input +full:- +full:pin (Results 1 – 25 of 713) sorted by relevance

12345678910>>...29

/Zephyr-latest/dts/bindings/pinctrl/
Dsilabs,dbus-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 The Silabs pin controller is a singleton node responsible for controlling
6 pin function selection and pin properties. For example, you can use this
7 node to route USART0 RX to pin PA1 and enable the pull-up resistor on the
8 pin. This pin controller is used for devices that use DBUS (Digital Bus)
15 compatible = "silabs,gecko-usart";
16 pinctrl-0 = <&usart0_default>;
17 pinctrl-names = "default";
20 pinctrl-0 is a phandle that stores the pin settings for the peripheral, in
22 'pinctrl' node, typically in a board-pinctrl.dtsi file in the board
[all …]
Dpincfg-node.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Generic pin configuration schema
7 Many data items that are represented in a pin configuration node are
8 common and generic. Pin control bindings should use the properties
16 https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
19 bias-disable:
21 description: disable any pin bias
23 bias-high-impedance:
25 description: high impedance mode ("third-state", "floating")
27 bias-bus-hold:
[all …]
Dti,cc13xx-cc26xx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 Device pin configuration should be placed in the child nodes of this node.
8 Populate the 'pinmux' field with a pair consisting of a pin number and its IO
18 All device pin configurations should be placed in child nodes of the
22 supported standard pin properties:
24 - bias-disable: Disable pull-up/down.
25 - bias-pull-down: Enable pull-down resistor.
26 - bias-pull-up: Enable pull-up resistor.
27 - drive-open-drain: Output driver is open-drain.
28 - drive-open-drain: Output driver is open-source.
[all …]
Dinfineon,xmc4xxx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 The Infineon XMC4XXX pin controller is responsible for connecting peripheral outputs
6 to specific port/pins (also known as alternate functions) and configures pin properties.
12 compatible = "infineon,xmc4xxx-uart";
13 pinctrl-0 = <&uart_tx_p0_1_u1c1 &uart_rx_p0_0_u1c1>;
14 pinctrl-names = "default";
15 input-src = "DX0D";
19 pinctrl-0 is the phandle that stores the pin settings for two pins: &uart_tx_p0_1_u1c1
20 and &uart_rx_p0_0_u1c1. These nodes are pre-defined and their naming convention is designed
21 to help the user select the correct pin settings. Note the use of peripheral type,
[all …]
Draspberrypi,pico-pinctrl.yaml3 # SPDX-License-Identifier: Apache-2.0
6 The RPi Pico pin controller is a node responsible for controlling
7 pin function selection and pin properties, such as routing a UART0 Rx
8 to pin 1 and enabling the pullup resistor on that pin.
17 All device pin configurations should be placed in child nodes of the
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
39 /* enable input on pin 1 */
40 input-enable;
[all …]
Dinfineon,cat1-pinctrl.yaml4 # SPDX-License-Identifier: Apache-2.0
9 This is a singleton node responsible for controlling the pin function selection
10 and pin properties. For example, you can use this node to route
11 UART0 RX to a particular port/pin and enable the pull-up resistor on that
12 pin.
21 Pin configuration can also specify the pin properties, for example the
22 'bias-pull-up' property. Here is a list of the supported standard pin
24 * bias-high-impedance
25 * bias-pull-up
26 * bias-pull-down
[all …]
Dnuvoton,numicro-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Nuvoton NuMicro pinctrl node. This node will define pin configurations in pin groups,
7 within the pin configuration defines the pin configuration for a peripheral,
8 and each numbered subgroup in the pin group defines all the pins for that
19 compatible: "nuvoton,numicro-pinctrl"
27 child-binding:
28 description: NuMicro pin controller pin group
29 child-binding:
31 NuMicro pin controller pin configuration node
33 - name: pincfg-node.yaml
[all …]
Dnxp,s32k3-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The NXP S32 pin controller is a singleton node responsible for controlling
8 the pin function selection and pin properties. This node, labeled 'pinctrl' in
9 the SoC's devicetree, will define pin configurations in pin groups. Each group
10 within the pin configuration defines the pin configuration for a peripheral,
11 and each numbered subgroup in the pin group defines all the pins for that
20 #include <nxp/s32/S32K344-257BGA-pinctrl.h>
26 output-enable;
30 input-enable;
35 The 'uart0_default' node contains the pin configurations for a particular state
[all …]
Drenesas,ra-pincrl-pfs.yaml2 # SPDX-License-Identifier: Apache-2.0
5 The Renesas RA pin controller is a node responsible for controlling
6 pin function selection and pin properties, such as routing a SCI0 RXD
16 All device pin configurations should be placed in child nodes of the
19 /* You can put this in places like a board-pinctrl.dtsi file in
23 /* include pre-defined combinations for the SoC variant used by the board */
24 #include <dt-bindings/pinctrl/renesas/pinctrl-ra.h>
32 drive-strength = "medium";
41 The 'sci0_default' child node encodes the pin configurations for a
45 As shown, pin configurations are organized in groups within each child node.
[all …]
Dnuvoton,npcx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 The Nuvoton pin controller is a singleton node responsible for controlling
6 pin function selection and pin properties. For example, you can use these
7 nodes to select peripheral pin functions.
9 Here is a list of supported standard pin properties:
10 - bias-pull-down: Enable pull-down resistor.
11 - bias-pull-up: Enable pull-up resistor.
12 - drive-open-drain: Output driver is open-drain.
14 Custom pin properties for npcx series are available also:
15 - pinmux-locked: Lock pinmux configuration for peripheral device
[all …]
Drenesas,rzt2m-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 The Renesas RZ/T2M pin controller is a node responsible for controlling
6 pin function selection and pin properties, such as routing the TX and RX of UART0
7 to pin 5 and pin 6 of port 16.
16 All device pin configurations should be placed in child nodes of the
19 /* You can put this in places like a board-pinctrl.dtsi file in
23 /* include pre-defined combinations for the SoC variant used by the board */
24 #include <dt-bindings/pinctrl/renesas-rzt2m-pinctrl.h>
33 input-enable;
38 The 'uart0_default' child node encodes the pin configurations for a
[all …]
Dnxp,imx93-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 the imx_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
15 bias-pull-up;
16 slew-rate = "slow";
17 drive-strength = "x1";
26 input-schmitt-enable: HYS=1
27 drive-open-drain: OD=1
28 bias-pull-down: PD=0
29 bias-pull-up: PU
30 slew-rate: FSEL1=<enum_idx>
[all …]
Dnxp,imx8mp-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 the imx_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
15 bias-pull-up;
16 slew-rate = "slow";
17 drive-strength = "x1";
26 input-schmitt-enable: HYS=1
27 bias-pull-up: PUE=1, PE=1
28 bias-pull-down: PUE=0, PE=1
29 drive-open-drain: ODE=1
30 slew-rate: FSEL=<enum_idx>
[all …]
Dnxp,imx7d-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 the imx_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
14 bias-pull-up: PE=1, PS=<bias-pull-up-value index>
15 bias-pull-down: PE=1, PS=0
16 input-schmitt-enable: HYS=1
17 slew-rate: SRE=<enum idx>
18 drive-strength: DSE=<enum idx>
19 input-enable: SION=1 (in SW_PAD_CTL_MUX register)
21 If only required properties are supplied, the pin will have the following
26 SRE=<slew-rate>,
[all …]
/Zephyr-latest/tests/drivers/gpio/gpio_api_1pin/src/
Dtest_config.c4 * SPDX-License-Identifier: Apache-2.0
16 unsigned int pin, in pin_get_raw_and_verify() argument
21 val_actual = gpio_pin_get_raw(port, pin); in pin_get_raw_and_verify()
23 "Test point %d: failed to get pin value", idx); in pin_get_raw_and_verify()
25 "Test point %d: invalid pin get value", idx); in pin_get_raw_and_verify()
29 unsigned int pin, in pin_set_raw_and_verify() argument
32 zassert_equal(gpio_pin_set_raw(port, pin, val), 0, in pin_set_raw_and_verify()
33 "Test point %d: failed to set pin value", idx); in pin_set_raw_and_verify()
39 * - Configure pin in in/out mode, verify that gpio_pin_set_raw /
40 * gpio_pin_get_raw operations change pin state.
[all …]
/Zephyr-latest/dts/bindings/mfd/
Dnordic,npm6001.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: i2c-device.yaml
14 nordic,ready-high-drive:
16 description: Set drive strength to high for READY pin.
18 nordic,nint-high-drive:
20 description: Set drive strength to high for NINT pin.
22 nordic,sda-high-drive:
24 description: Set drive strength to high for SDA pin.
26 nordic,buck-mode0-input-type:
30 description: Input type for BUCK_MODE0 pin. Defaults IC boot-time value.
[all …]
/Zephyr-latest/boards/infineon/cy8cproto_062_4343w/
Dcy8cproto_062_4343w-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
6 /* Configure pin control bias mode for uart2 pins */
8 drive-push-pull;
12 input-enable;
16 drive-push-pull;
20 input-enable;
23 /* Configure pin control bias mode for uart5 pins */
25 drive-push-pull;
29 input-enable;
32 /* Configure pin control bias mode for i2c3 pins */
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/gpio/
Despressif-esp32-gpio.h4 * SPDX-License-Identifier: Apache-2.0
17 * `DFLT` - The lowest drive strength supported by the HW
18 * `ALT` - The highest drive strength supported by the HW
36 * @name GPIO pin input/output enable flags
38 * These flags allow configuring a pin as input or output while keeping untouched
39 * its complementary configuration. By instance, if we configure a GPIO pin as an
40 * input and pass the flag ESP32_GPIO_PIN_OUT_EN, the driver will not disable the
41 * pin's output buffer. This functionality can be useful to render a pin both an
42 * input and output, for diagnose or testing purposes.
47 /** Keep GPIO pin enabled as output */
[all …]
/Zephyr-latest/dts/bindings/video/
Dnxp,video-smartdma.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,video-smartdma"
8 include: [base.yaml, pinctrl-device.yaml]
15 vsync-pin:
19 GPIO0 pin index to use for VSYNC input. Only pins 0-15 may be used.
20 hsync-pin:
24 GPIO0 pin index to use for HSYNC input. Only pins 0-15 may be used.
25 pclk-pin:
29 GPIO0 pin index to use for PCLK input. Only pins 0-15 may be used.
/Zephyr-latest/dts/bindings/gpio/
Dti,tca9538.yaml3 # SPDX-License-Identifier: Apache-2.0
9 include: [i2c-device.yaml, gpio-controller.yaml]
12 "#gpio-cells":
21 nint-gpios:
22 type: phandle-array
24 Connection for the NINT signal. This signal is active-low when
27 input-latch:
30 Input latch register bit is 0 by default and the input pin state
31 is not latched. When input latch register bit is 1 and the input
32 pin state is latched.
[all …]
Darduino-header-r3.yaml3 # SPDX-License-Identifier: Apache-2.0
11 Proceeding counter-clockwise:
12 * An 8-pin Power Supply header. No pins on this header are exposed
14 * A 6-pin Analog Input header. This has analog input signals
16 * An 8-pin header (opposite Analog Input). This has digital input
18 * A 10-pin header (opposite Power Supply). This has six additional
19 digital input signals labelled from D8 at the bottom through D13
29 AREF -
30 GND -
31 - N/C D13 19
[all …]
/Zephyr-latest/soc/atmel/sam0/common/
Dsoc_port.h2 * Copyright (c) 2016-2017 Piotr Mienkowski
3 * Copyright (c) 2020-2022 Gerson Fernando Budke
4 * SPDX-License-Identifier: Apache-2.0
8 * @brief Atmel SAM0 MCU family I/O Pin Controller (PORT)
17 * Pin flags/attributes
27 /* Open-Drain is a reserved entry at pinctrl driver */
29 /* Input-Enable means Input-Buffer, see dts/pinctrl/pincfg-node.yaml */
32 /* Output-Enable, see dts/pinctrl/pincfg-node.yaml */
35 /* Drive-Strength, 0mA means normal, any other value means stronger */
46 /** Connect pin to peripheral A. */
[all …]
/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Dwuc_ite_it8xxx2.h4 * SPDX-License-Identifier: Apache-2.0
14 * @brief A trigger condition on the corresponding input generates
15 * a wake-up signal to the power management control of EC
18 * @param mask Pin mask of WUC group
23 * @brief A trigger condition on the corresponding input doesn't
24 * assert the wake-up signal (canceled not pending)
27 * @param mask Pin mask of WUC group
32 * @brief Write-1-clear a trigger condition that occurs on the
33 * corresponding input
36 * @param mask Pin mask of WUC group
[all …]
/Zephyr-latest/samples/drivers/adc/adc_dt/boards/
Dlpcxpresso55s69_lpc55s69_cpu0.overlay2 * SPDX-License-Identifier: Apache-2.0
4 * Copyright 2022-2024 NXP
7 #include <zephyr/dt-bindings/adc/mcux-lpadc.h>
11 io-channels = <&adc0 0 &adc0 1 &adc0 2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 * - Connect VREFN_TARGET to GND, and VREFP_TARGET to 3v3
24 * - Connect LPADC0 CH0A signal to voltage between 0~3.3V (P19 pin 4)
25 * - Connect LPADC0 CH0B signal to voltage between 0~3.3V (P19 pin 2)
27 * - Connect LPADC0 CH4A signal to voltage between 0~3.3V (P17 pin 19)
[all …]
/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dsoc.h2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
11 * This header file is used to specify and describe board-level aspects for the
32 /*!<@brief Selects pin function 0 */
34 /*!<@brief Selects pin function 1 */
36 /*!<@brief Selects pin function 2 */
38 /*!<@brief Selects pin function 3 */
40 /*!<@brief Selects pin function 4 */
42 /*!<@brief Selects pin function 5 */
44 /*!<@brief Selects pin function 6 */
[all …]

12345678910>>...29