Lines Matching +full:input +full:- +full:pin

2 # SPDX-License-Identifier: Apache-2.0
7   the imx_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
15       bias-pull-up;
16       slew-rate = "slow";
17       drive-strength = "x1";
26   input-schmitt-enable: HYS=1
27   bias-pull-up: PUE=1, PE=1
28   bias-pull-down: PUE=0, PE=1
29   drive-open-drain: ODE=1
30   slew-rate: FSEL=<enum_idx>
31   drive-strength: DSE=<enum_idx>
32   input-enable: SION=1 (in SW_MUX_CTL_PAD register)
34   If only required properties are supplied, the pin will have the following
40   SRE=<slew-rate>,
41   DSE=<drive-strength>,
45 compatible: "nxp,imx8mp-pinctrl"
49 child-binding:
50   description: iMX pin controller pin group
51   child-binding:
53       iMX pin controller pin configuration node.
56       - name: pincfg-node.yaml
57         property-allowlist:
58           - input-schmitt-enable
59           - drive-open-drain
60           - input-enable
61           - bias-pull-up
62           - bias-pull-down
69           Pin mux selections for this group. See the soc level iomuxc DTSI file
71       drive-strength:
75           - "x1"
76           - "x4"
77           - "x2"
78           - "x6"
80           Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
81           00 X1- low drive strength
82           01 X4- high drive strength
83           10 X2- medium drive strength
84           11 X6- max drive strength
85       slew-rate:
89           - "slow"
90           - "fast"
92           Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral