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/Zephyr-latest/dts/bindings/display/panel/
Dpanel-timing.yaml2 # SPDX-License-Identifier: Apache-2.0
9 a panel under display-timings node. For example:
12 display-timings {
13 compatible = "zephyr,panel-timing";
14 hsync-len = <8>;
15 hfront-porch = <32>;
16 hback-porch = <32>;
17 vsync-len = <2>;
18 vfront-porch = <16>;
19 vback-porch = <14>;
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/Zephyr-latest/dts/bindings/video/
Dst,stm32-dcmi.yaml4 # SPDX-License-Identifier: Apache-2.0
14 pinctrl-0 = <&dcmi_hsync_pa4 &dcmi_pixclk_pa6 &dcmi_vsync_pb7
17 pinctrl-names = "default";
18 bus-width = <8>;
19 hsync-active = <0>;
20 vsync-active = <0>;
21 pixelclk-active = <1>;
22 capture-rate = <1>;
29 remote-endpoint = <&ov2640_ep_out>;
34 compatible: "st,stm32-dcmi"
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Dvideo-interfaces.yaml2 # SPDX-License-Identifier: Apache-2.0
16 scheme using '#address-cells', '#size-cells' and 'reg' properties is used.
19 specify #address-cells, #size-cells properties independently for the 'port' and
25 #address-cells = <1>;
26 #size-cells = <0>;
37 Two 'endpoint' nodes must be linked with each other via their 'remote-endpoint'
39 references are currently not possible. A 'remote-endpoint-label' string is used
40 instead to be able to specify, at least, the label of the peer remote-endpoint.
44 compatible = "zephyr,video-interfaces";
45 remote-endpoint-label = "sink";
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/Zephyr-latest/boards/shields/rk043fn02h_ct/
Drk043fn02h_ct.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
16 compatible = "zephyr,lvgl-pointer-input";
26 int-gpios = <&nxp_i2c_touch_fpc 2 GPIO_ACTIVE_LOW>;
34 display-timings {
35 compatible = "zephyr,panel-timing";
36 hsync-len = <41>;
37 hfront-porch = <4>;
38 hback-porch = <8>;
39 vsync-len = <10>;
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/Zephyr-latest/boards/shields/rk043fn66hs_ctg/
Drk043fn66hs_ctg.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
16 compatible = "zephyr,lvgl-pointer-input";
26 irq-gpios = <&nxp_i2c_touch_fpc 2 GPIO_ACTIVE_HIGH>;
27 reset-gpios = <&nxp_i2c_touch_fpc 1 GPIO_ACTIVE_LOW>;
35 display-timings {
36 compatible = "zephyr,panel-timing";
37 hsync-len = <4>;
38 hfront-porch = <8>;
39 hback-porch = <43>;
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/Zephyr-latest/boards/shields/rk055hdmipi4ma0/
Drk055hdmipi4ma0.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
15 en_mipi_display_rk055hdmipi4ma0: enable-mipi-display-rk055hdmipi4ma0 {
16 compatible = "regulator-fixed";
17 regulator-name = "en_mipi_display";
18 enable-gpios = <&nxp_mipi_connector 32 GPIO_ACTIVE_HIGH>;
19 regulator-boot-on;
23 compatible = "zephyr,lvgl-pointer-input";
30 gt911_rk055hdmipi4ma0: gt911-rk055hdmipi4ma0@5d {
33 irq-gpios = <&nxp_mipi_connector 29 GPIO_ACTIVE_HIGH>;
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/Zephyr-latest/boards/shields/rk055hdmipi4m/
Drk055hdmipi4m.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
15 en_mipi_display: enable-mipi-display {
16 compatible = "regulator-fixed";
17 regulator-name = "en_mipi_display";
18 enable-gpios = <&nxp_mipi_connector 32 GPIO_ACTIVE_HIGH>;
19 regulator-boot-on;
23 compatible = "zephyr,lvgl-pointer-input";
33 irq-gpios = <&nxp_mipi_connector 29 GPIO_ACTIVE_HIGH>;
34 reset-gpios = <&nxp_mipi_connector 28 GPIO_ACTIVE_LOW>;
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/Zephyr-latest/boards/shields/rtkmipilcdb00000be/
Drtkmipilcdb00000be.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
15 compatible = "zephyr,lvgl-pointer-input";
22 gt911_rtkmipilcdb00000be: gt911-rtkmipilcdb00000be@5d {
25 irq-gpios = <&renesas_mipi_connector 17 GPIO_ACTIVE_HIGH>;
26 reset-gpios = <&renesas_mipi_connector 18 GPIO_ACTIVE_LOW>;
34 compatible = "ilitek,ili9806e-dsi";
38 data-lanes = <2>;
39 pixel-format = <MIPI_DSI_PIXFMT_RGB888>;
47 input-pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
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/Zephyr-latest/boards/shields/st_b_lcd40_dsi1_mb1166/
Dst_b_lcd40_dsi1_mb1166.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
11 compatible = "zephyr,lvgl-pointer-input";
13 invert-y;
29 reset-gpios = <&dsi_lcd_qsh_030 57 GPIO_ACTIVE_HIGH>;
30 bl-gpios = <&dsi_lcd_qsh_030 53 GPIO_ACTIVE_HIGH>;
31 data-lanes = <2>;
32 pixel-format = <MIPI_DSI_PIXFMT_RGB888>;
41 pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
43 display-timings {
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Dst_b_lcd40_dsi1_mb1166_a09.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
11 compatible = "zephyr,lvgl-pointer-input";
13 invert-y;
29 reset-gpios = <&dsi_lcd_qsh_030 57 GPIO_ACTIVE_HIGH>;
30 bl-gpios = <&dsi_lcd_qsh_030 53 GPIO_ACTIVE_HIGH>;
31 data-lanes = <2>;
32 pixel-format = <MIPI_DSI_PIXFMT_RGB888>;
41 pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
43 display-timings {
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/Zephyr-latest/boards/renesas/da1469x_dk_pro/dts/
Dda1469x_dk_pro_lcdc.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
8 #include <zephyr/dt-bindings/display/panel.h>
19 swap-xy;
28 bias-pull-up;
36 bias-pull-up;
42 clock-frequency = <400000>;
49 int-gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
55 pinctrl-0 = <&display_controller_default>;
56 pinctrl-1 = <&display_controller_sleep>;
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/Zephyr-latest/boards/shields/weact_ov2640_cam_module/
Dweact_ov2640_cam_module.overlay4 * SPDX-License-Identifier: Apache-2.0
15 clock-frequency = <I2C_BITRATE_FAST>;
24 remote-endpoint = <&zephyr_camera_dvp_in>;
33 bus-width = <8>;
34 hsync-active = <0>;
35 vsync-active = <0>;
36 pixelclk-active = <1>;
37 capture-rate = <1>;
41 remote-endpoint = <&ov2640_ep_out>;
/Zephyr-latest/dts/bindings/display/
Dftdi,ft800.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: spi-device.yaml
11 irq-gpios:
12 type: phandle-array
35 Controls the transition of RGB signals with PCLK active clock
37 following the active edge of PCLK. When set to 1, R[7:2]
100 description: Number of PCLK cycles of HSYNC high state during start of
106 description: Number of PCLK cycles for HSYNC toggle during start of line.
/Zephyr-latest/include/zephyr/drivers/
Dmipi_dsi.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Public APIs for MIPI-DSI drivers
16 * @brief MIPI-DSI driver APIs
17 * @defgroup mipi_dsi_interface MIPI-DSI driver APIs
27 #include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
33 /** MIPI-DSI display timings. */
35 /** Horizontal active video. */
42 uint32_t hsync; member
43 /** Vertical active video. */
54 * @name MIPI-DSI Device mode flags.
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/Zephyr-latest/boards/st/stm32f746g_disco/
Dstm32f746g_disco.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f7/stm32f746nghx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include <zephyr/dt-bindings/memory-attr/memory-attr.h>
13 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
17 compatible = "st,stm32f746g-disco";
21 zephyr,shell-uart = &usart1;
25 zephyr,flash-controller = &n25q128a1;
31 compatible = "gpio-leds";
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/Zephyr-latest/boards/st/stm32f429i_disc1/
Dstm32f429i_disc1.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
10 #include <st/f4/stm32f429zitx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/display/ili9xxx.h>
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
20 zephyr,shell-uart = &usart1;
29 compatible = "zephyr,memory-region", "mmio-sram";
32 zephyr,memory-region = "SDRAM2";
36 compatible = "gpio-leds";
48 compatible = "gpio-keys";
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/Zephyr-latest/boards/st/stm32f7508_dk/
Dstm32f7508_dk.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
10 #include <st/f7/stm32f750n8hx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
13 #include <zephyr/dt-bindings/input/input-event-codes.h>
16 model = "STMicroelectronics STM32F7508-DK";
21 zephyr,shell-uart = &usart1;
25 zephyr,flash-controller = &n25q128a1;
31 compatible = "gpio-leds";
39 compatible = "gpio-keys";
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/Zephyr-latest/boards/st/stm32h750b_dk/
Dstm32h750b_dk.dts2 * Copyright (c) 2023-2024 STMicroelectronics
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/h7/stm32h750xbhx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 compatible = "st,stm32h750b-dk";
19 zephyr,shell-uart = &usart3;
22 zephyr,flash-controller = &mt25ql512ab1;
27 compatible = "zephyr,memory-region", "mmio-sram";
30 zephyr,memory-region = "SDRAM2";
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/Zephyr-latest/boards/st/stm32h7b3i_dk/
Dstm32h7b3i_dk.dts2 * Copyright (c) 2022 Byte-Lab d.o.o. <dev@byte-lab.com>
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/h7/stm32h7b3lihxq-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
16 compatible = "st,stm32h7b3i-dk";
20 zephyr,shell-uart = &usart1;
29 compatible = "gpio-leds";
41 compatible = "gpio-keys";
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/Zephyr-latest/boards/witte/linum/
Dlinum.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/h7/stm32h753bitx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
18 zephyr,shell-uart = &usart1;
22 zephyr,code-partition = &slot0_partition;
27 compatible = "zephyr,memory-region", "mmio-sram";
30 zephyr,memory-region = "SDRAM1";
31 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
35 compatible = "gpio-leds";
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/Zephyr-latest/boards/arduino/nicla_vision/
Darduino_nicla_vision_stm32h747xx_m7.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/h7/stm32h747a(g-i)ix-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
15 compatible = "arduino,nicla-vision";
19 zephyr,shell-uart = &lpuart1;
20 zephyr,uart-mcumgr = &lpuart1;
21 zephyr,bt-hci = &bt_hci_uart;
24 zephyr,code-partition = &slot0_partition;
34 compatible = "usb-ulpi-phy";
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/Zephyr-latest/boards/nxp/frdm_mcxn947/
Dboard.c3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
32 /* Update Active mode voltage for OverDrive mode. */
61 SYSCON->AHBCLKCTRLSET[0] |= SYSCON_AHBCLKCTRL0_FLEXSPI_MASK; in enable_cache64()
64 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK; in enable_cache64()
65 CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK; in enable_cache64()
67 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) { in enable_cache64()
70 CACHE64_CTRL0->CCR = (CACHE64_CTRL_CCR_ENWRBUF_MASK | CACHE64_CTRL_CCR_ENCACHE_MASK); in enable_cache64()
76 CACHE64_POLSEL0->REG0_TOP = 0x7FFC00; in enable_cache64()
77 CACHE64_POLSEL0->REG1_TOP = 0x0; in enable_cache64()
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/Zephyr-latest/drivers/display/
Ddisplay_ili9806e_dsi.c4 * SPDX-License-Identifier: Apache-2.0
42 /* DE = 1 Active */
50 /* avdd +5.2v,avee-5.2v */
52 /* VGL=DDVDL+VCL-VCIP,VGH=2DDVDH-DDVDL */
213 const struct ili9806e_config *cfg = dev->config; in ili9806e_write_reg()
215 ret = mipi_dsi_dcs_write(cfg->mipi_dsi, cfg->channel, reg, buf, len); in ili9806e_write_reg()
236 ret = ili9806e_write_reg(dev, cmd->reg, cmd->cmd, cmd->cmd_len); in ili9806e_write_sequence()
238 LOG_ERR("Failed writing sequence: 0x%x result: (%d)", cmd->reg, ret); in ili9806e_write_sequence()
249 const struct ili9806e_config *cfg = dev->config; in ili9806e_config()
270 cfg->pixel_format == PIXEL_FORMAT_RGB_565 in ili9806e_config()
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