| /Zephyr-latest/dts/bindings/gpio/ |
| D | ene,kb1200-gpio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 ENE KB1200 GPIO(General purpose IO) Port node
7 The GPIO controller provides group control of GPIO functions. Each port
8 group contains 32 pins. GPIO_00~GPIO_1F belong to the Port0 group,
9 GPIO_20~GPIO_3F belong to the Port1 group, and so on.
11 In particular, the 32 pins of the port group do not share the same IRQ
13 pins. This means that single port group provide two interrupt source.
14 ex.Port0 group GPIO_00~GPIO_0F shares IRQ18, and Port0 group
17 compatible: "ene,kb1200-gpio"
19 include: [gpio-controller.yaml, base.yaml]
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| D | intel,gpio.yaml | 1 # Copyright (c) 2018-2019 Intel Corporation
2 # SPDX-License-Identifier: Apache-2.0
4 description: Intel GPIO node
6 compatible: "intel,gpio"
8 include: [acpi.yaml, gpio-controller.yaml, base.yaml]
14 group-index:
16 description: Group number for this GPIO entry
22 description: Number of pins for this GPIO entry
24 pin-offset:
26 description: Pin offset of this GPIO entry
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| D | nxp,gpio-cluster.yaml | 1 description: A group of GPIOs that share an interrupt.
3 compatible: "nxp,gpio-cluster"
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | silabs,dbus-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 node to route USART0 RX to pin PA1 and enable the pull-up resistor on the
15 compatible = "silabs,gecko-usart";
16 pinctrl-0 = <&usart0_default>;
17 pinctrl-names = "default";
20 pinctrl-0 is a phandle that stores the pin settings for the peripheral, in
22 'pinctrl' node, typically in a board-pinctrl.dtsi file in the board
28 /* Group of output pins with shared properties (name is arbitrary) */
30 /* Configure PA8 as USART0 TX in GPIO DBUS */
32 /* Configure GPIO to push-pull mode */
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| D | ite,it8xxx2-pinctrl-func.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "ite,it8xxx2-pinctrl-func"
11 func3-gcr:
14 func3-en-mask:
17 func3-ext:
21 the setting of func3-gcr, some pins require external setting.
23 func3-ext-mask:
26 func4-gcr:
29 func4-en-mask:
32 volt-sel:
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| D | nxp,s32ze-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 the SoC's devicetree, will define pin configurations in pin groups. Each group
11 and each numbered subgroup in the pin group defines all the pins for that
13 a group selects the pins to be configured, and the remaining properties set
20 #include <nxp/s32/S32Z27-BGA594-pinctrl.h>
26 output-enable;
30 input-enable;
39 In addition to 'pinmux' property, each group can contain other properties such as
40 'bias-pull-up' or 'slew-rate' that will be applied to all the pins defined in
41 'pinmux' array. To enable the input buffer use 'input-enable' and to enable the
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| /Zephyr-latest/dts/x86/intel/ |
| D | raptor_lake_p.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/pcie/pcie.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "intel,raptor-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 interrupt-controller;
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| D | elkhart_lake.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,elkhart-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
38 #address-cells = <1>;
39 #interrupt-cells = <3>;
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| D | raptor_lake_s.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/pcie/pcie.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,raptor-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
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| /Zephyr-latest/dts/bindings/led/ |
| D | gpio-leds.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 This allows you to define a group of LEDs. Each LED in the group is
6 controlled by a GPIO. Each LED is defined in a child node of the
7 gpio-leds node.
13 compatible = "gpio-leds";
28 - led_0 is pin 1 on gpio0. The LED is on when the pin is low,
30 - led_1 is pin 2 on gpio0. The LED is on when the pin is high,
32 - led_2 is pin 15 on gpio1. The LED is on when the pin is low,
33 and the pin's internal pull-up resistor should be enabled.
35 compatible: "gpio-leds"
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_miwu.c | 4 * SPDX-License-Identifier: Apache-2.0
13 * The device Multi-Input Wake-Up Unit (MIWU) supports the Nuvoton embedded
19 * wake-up input (WUI) sources.
24 * 1. npcxn-miwus-wui-map.dtsi: it presents relationship between wake-up inputs
25 * (WUI) and its source device such as gpio, timer, eSPI VWs and so on.
26 * 2. npcxn-miwus-int-map.dtsi: it presents relationship between MIWU group
27 * and NVIC interrupt in npcx series. Please notice it isn't 1-to-1 mapping.
28 * For example, here is the mapping between miwu0's group a & d and IRQ7:
41 * 0x09, the driver checks the pending bits of group a and group d in ISR.
54 #include <zephyr/drivers/gpio.h>
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| /Zephyr-latest/dts/bindings/ethernet/ |
| D | davicom,dm8806-phy.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "davicom,dm8806-phy"
8 include: [ethernet-phy.yaml]
10 on-bus: mdio
16 5-bit PHY address for Internal PHY Registers group of Davicom DM8806 MAC
24 Register address are glued together in Internal PHY Registers group:
27 Port0: (5-bit PHY Address) + (5-bit Register address) = Absolute address
31 reg-switch:
34 5-bit PHY address for Switch Per-Port Registers group of Davicom DM8806
42 Register address are glued together in Switch Per-Port Registers group:
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| /Zephyr-latest/dts/riscv/ite/ |
| D | it8xxx2-wuc-map.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/dt-util.h>
11 it8xxx2-wuc-map {
12 compatible = "ite,it8xxx2-wuc-map";
14 /* WUC group 2 */
34 /* WUC group 3 */
60 /* WUC group 4 */
74 /* WUC group 5 */
100 /* WUC group 6 */
126 /* WUC group 7 */
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| D | it81xx2.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 gpiogcr: gpio-gcr@f01600 {
12 compatible = "ite,it8xxx2-gpiogcr";
17 compatible = "ite,it8xxx2-gpiokscan";
23 reg-names = "goen", "gctrl", "gdat", "gdmr", "gpod";
25 gpio-controller;
26 #gpio-cells = <2>;
30 compatible = "ite,it8xxx2-gpiokscan";
36 reg-names = "goen", "gctrl", "gdat", "gdmr", "gpod";
38 gpio-controller;
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| /Zephyr-latest/boards/arduino/opta/dts/bindings/ |
| D | gpio-power-switches.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 This allows to define a group of relays (like in the original Opta)
6 or other kinds of power switches controlled by a GPIO. Each power
7 switch is defined in a child node of the gpio-power-switches node.
9 compatible: "gpio-power-switches"
11 child-binding:
12 description: GPIO power switch child node
15 type: phandle-array
|
| /Zephyr-latest/drivers/gpio/ |
| D | gpio_bcm2711.c | 3 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/gpio.h>
11 #include <zephyr/drivers/gpio/gpio_utils.h>
42 #define DEV_CFG(dev) ((const struct gpio_bcm2711_config *const)(dev)->config)
43 #define DEV_DATA(dev) ((struct gpio_bcm2711_data *const)(dev)->data)
45 #define RPI_PIN_NUM(dev, n) (DEV_CFG(dev)->offset + n)
72 uint32_t group; in gpio_bcm2711_pin_configure() local
77 return -ENOTSUP; in gpio_bcm2711_pin_configure()
82 group = GPIO_REG_GROUP(RPI_PIN_NUM(port, pin), FSEL_GROUPS); in gpio_bcm2711_pin_configure()
85 regval = sys_read32(GPFSEL(data->base, group)); in gpio_bcm2711_pin_configure()
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| /Zephyr-latest/include/zephyr/dt-bindings/espi/ |
| D | npcx_espi.h | 4 * SPDX-License-Identifier: Apache-2.0
10 * Encode virtual wire information into a 16-bit unsigned.
12 * group = bits[11:8], Group number for VWEVMS or VWEVSM
15 #define ESPI_NPCX_VW_EX_VAL(dir, group, index) \ argument
16 (((dir & 0x1) << 12) + ((group & 0xf) << 8) + (index & 0xff))
51 /* eSPI VW GPIO Slave to Master Register Index */
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| /Zephyr-latest/soc/nuvoton/npcx/common/ |
| D | scfg.c | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/drivers/gpio.h>
9 #include <zephyr/dt-bindings/pinctrl/npcx-pinctrl.h>
28 * GPIO in pin-mux init function.
30 * def-io-conf-list {
37 .group = DT_PHA(DT_PROP_BY_IDX(node_id, prop, idx), alts, group), \
58 /* Pin-control local functions */
62 uint8_t alt_mask = BIT(alt->bit); in npcx_pinctrl_alt_sel()
65 * alt_fun == 0 means select GPIO, otherwise Alternate Func. in npcx_pinctrl_alt_sel()
71 if (!!alt_func != !!alt->inverted) { in npcx_pinctrl_alt_sel()
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| D | soc_miwu.h | 4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/drivers/gpio.h>
60 * @brief NPCX wake-up input source structure
62 * Used to indicate a Wake-Up Input source (WUI) belongs to which group and bit
63 * of Multi-Input Wake-Up Unit (MIWU) modules.
67 uint8_t group:3; /** A source belongs to which group of MIWU table. */ member
68 uint8_t bit:3; /** A source belongs to which bit of MIWU group. */
72 * Define npcx miwu driver callback handler signature for wake-up input source
80 * @brief MIWU/GPIO information structure
82 * It contains both GPIO and MIWU information which is stored in unused field
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| /Zephyr-latest/dts/bindings/i2c/ |
| D | st,stm32-i2c-v1.yaml | 1 # Copyright (c) 2017 I-SENSE group of ICCS
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "st,stm32-i2c-v1"
8 include: [i2c-controller.yaml, pinctrl-device.yaml]
17 pinctrl-0:
20 pinctrl-names:
23 scl-gpios:
24 type: phandle-array
26 GPIO to which the I2C SCL signal is routed. This is only needed for
29 sda-gpios:
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| /Zephyr-latest/doc/build/dts/ |
| D | phandles.rst | 1 .. _dt-phandles:
19 .. code-block:: DTS
22 lbl_a: node-1 {};
23 lbl_b: lbl_c: node-2 {};
28 - ``/node-1`` as ``&lbl_a``
29 - ``/node-2`` as either ``&lbl_b`` or ``&lbl_c``
40 :ref:`dt-bindings-properties` in the devicetree bindings documentation.
47 You can use phandles to refer to ``node-b`` from ``node-a``, where ``node-b``
48 is related to ``node-a`` in some way.
50 One common example is when ``node-a`` represents some hardware that
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| /Zephyr-latest/dts/bindings/input/ |
| D | gpio-keys.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Zephyr Input GPIO KEYS parent node
7 This defines a group of buttons that can generate input events. Each button
8 is defined in a child node of the gpio-keys node and defines a specific key
13 #include <zephyr/dt-bindings/input/input-event-codes.h>
17 compatible = "gpio-keys";
26 compatible: "gpio-keys"
31 debounce-interval-ms:
38 polling-mode:
42 specified debounce-interval-ms instead.
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| /Zephyr-latest/boards/adafruit/feather_nrf52840/doc/ |
| D | index.rst | 7 nRF52840 ARM Cortex-M4F CPU and the following devices:
12 * :abbr:`GPIO (General Purpose Input Output)`
13 * :abbr:`I2C (Inter-Integrated Circuit)`
21 * :abbr:`UART (Universal asynchronous receiver-transmitter)`
27 .. group-tab:: Express
33 .. group-tab:: Sense
42 - nRF52840 ARM Cortex-M4F processor at 64 MHz
43 - 1 MB flash memory and 256 KB of SRAM
44 - Battery connector and charger for 3.7 V lithium polymer batteries
45 - Charging indicator LED
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| /Zephyr-latest/soc/intel/common/ |
| D | soc_gpio.h | 4 * SPDX-License-Identifier: Apache-2.0
21 * @brief Retrieve current resource settings of a gpio device from acpi.
23 * @param bank_idx band index of the gpio group (eg: gpp_a, gpp_b etc.)
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| /Zephyr-latest/boards/renesas/ek_ra2a1/doc/ |
| D | index.rst | 9 The EK-RA2A1 is an evaluation kit for Renesas RA2A1 Microcontroller Group.
11 Renesas RA2A1 Microcontroller Group has following features
13 - 48MHz, Arm Cortex-M23 core
14 - 256kB Code Flash, 8kB Data Flash, 32kB SRAM
15 - USB 2.0 Full-Sppeed
16 - SCI x 3
17 - SPI x 2
18 - I2C x 2
19 - CAN x 1
20 - 16-bit A/D Converter
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