4  * SPDX-License-Identifier: Apache-2.0
13  * The device Multi-Input Wake-Up Unit (MIWU) supports the Nuvoton embedded
19  * wake-up input (WUI) sources.
24  *  1. npcxn-miwus-wui-map.dtsi: it presents relationship between wake-up inputs
25  *     (WUI) and its source device such as gpio, timer, eSPI VWs and so on.
26  *  2. npcxn-miwus-int-map.dtsi: it presents relationship between MIWU group
27  *     and NVIC interrupt in npcx series. Please notice it isn't 1-to-1 mapping.
28  *     For example, here is the mapping between miwu0's group a & d and IRQ7:
41  *     0x09, the driver checks the pending bits of group a and group d in ISR.
54 #include <zephyr/drivers/gpio.h>
83 	/* Callback functions list for each MIWU group */
109 		if (cb->io_cb.params.cb_type == NPCX_MIWU_CALLBACK_GPIO) {  in intc_miwu_dispatch_isr()
110 			if (BIT(cb->io_cb.params.wui.bit) & mask) {  in intc_miwu_dispatch_isr()
111 				__ASSERT(cb->io_cb.handler, "No GPIO callback handler!");  in intc_miwu_dispatch_isr()
112 				cb->io_cb.handler(  in intc_miwu_dispatch_isr()
113 					npcx_get_gpio_dev(cb->io_cb.params.gpio_port),  in intc_miwu_dispatch_isr()
115 					cb->io_cb.params.pin_mask);  in intc_miwu_dispatch_isr()
118 			if (BIT(cb->dev_cb.params.wui.bit) & mask) {  in intc_miwu_dispatch_isr()
119 				__ASSERT(cb->dev_cb.handler, "No device callback handler!");  in intc_miwu_dispatch_isr()
121 				cb->dev_cb.handler(cb->dev_cb.params.source,  in intc_miwu_dispatch_isr()
122 						   &cb->dev_cb.params.wui);  in intc_miwu_dispatch_isr()
129 static void npcx_miwu_set_pseudo_both_edge(uint8_t table, uint8_t group, uint8_t bit)  in npcx_miwu_set_pseudo_both_edge()  argument
131 	const struct intc_miwu_config *config = miwu_devs[table]->config;  in npcx_miwu_set_pseudo_both_edge()
132 	const uint32_t base = config->base;  in npcx_miwu_set_pseudo_both_edge()
135 	if (IS_BIT_SET(NPCX_WKST(base, group), bit)) {  in npcx_miwu_set_pseudo_both_edge()
137 		NPCX_WKEDG(base, group) |= pmask;  in npcx_miwu_set_pseudo_both_edge()
140 		NPCX_WKEDG(base, group) &= ~pmask;  in npcx_miwu_set_pseudo_both_edge()
147 	const struct intc_miwu_config *config = miwu_devs[wui_table]->config;  in intc_miwu_isr_pri()
148 	struct intc_miwu_data *data = miwu_devs[wui_table]->data;  in intc_miwu_isr_pri()
149 	const uint32_t base = config->base;  in intc_miwu_isr_pri()
156 		uint8_t pending_bit = find_lsb_set(new_mask) - 1;  in intc_miwu_isr_pri()
160 		if ((data->both_edge_pins[wui_group] & pending_mask) != 0) {  in intc_miwu_isr_pri()
173 	/* Dispatch registered gpio isrs */  in intc_miwu_isr_pri()
174 	intc_miwu_dispatch_isr(&data->cb_list_grp[wui_group], mask);  in intc_miwu_isr_pri()
180 	const struct intc_miwu_config *config = miwu_devs[wui->table]->config;  in npcx_miwu_irq_enable()
181 	const uint32_t base = config->base;  in npcx_miwu_irq_enable()
185 	struct intc_miwu_data *data = miwu_devs[wui->table]->data;  in npcx_miwu_irq_enable()
187 	key = k_spin_lock(&data->lock);  in npcx_miwu_irq_enable()
190 	NPCX_WKEN(base, wui->group) |= BIT(wui->bit);  in npcx_miwu_irq_enable()
193 	if ((data->both_edge_pins[wui->group] & BIT(wui->bit)) != 0) {  in npcx_miwu_irq_enable()
194 		npcx_miwu_set_pseudo_both_edge(wui->table, wui->group, wui->bit);  in npcx_miwu_irq_enable()
196 	k_spin_unlock(&data->lock, key);  in npcx_miwu_irq_enable()
202 	const struct intc_miwu_config *config = miwu_devs[wui->table]->config;  in npcx_miwu_irq_disable()
203 	const uint32_t base = config->base;  in npcx_miwu_irq_disable()
205 	NPCX_WKEN(base, wui->group) &= ~BIT(wui->bit);  in npcx_miwu_irq_disable()
210 	const struct intc_miwu_config *config = miwu_devs[wui->table]->config;  in npcx_miwu_io_enable()
211 	const uint32_t base = config->base;  in npcx_miwu_io_enable()
213 	NPCX_WKINEN(base, wui->group) |= BIT(wui->bit);  in npcx_miwu_io_enable()
218 	const struct intc_miwu_config *config = miwu_devs[wui->table]->config;  in npcx_miwu_io_disable()
219 	const uint32_t base = config->base;  in npcx_miwu_io_disable()
221 	NPCX_WKINEN(base, wui->group) &= ~BIT(wui->bit);  in npcx_miwu_io_disable()
226 	const struct intc_miwu_config *config = miwu_devs[wui->table]->config;  in npcx_miwu_irq_get_state()
227 	const uint32_t base = config->base;  in npcx_miwu_irq_get_state()
229 	return IS_BIT_SET(NPCX_WKEN(base, wui->group), wui->bit);  in npcx_miwu_irq_get_state()
234 	const struct intc_miwu_config *config = miwu_devs[wui->table]->config;  in npcx_miwu_irq_get_and_clear_pending()
235 	const uint32_t base = config->base;  in npcx_miwu_irq_get_and_clear_pending()
238 	struct intc_miwu_data *data = miwu_devs[wui->table]->data;  in npcx_miwu_irq_get_and_clear_pending()
241 	bool pending = IS_BIT_SET(NPCX_WKPND(base, wui->group), wui->bit);  in npcx_miwu_irq_get_and_clear_pending()
245 		key = k_spin_lock(&data->lock);  in npcx_miwu_irq_get_and_clear_pending()
247 		NPCX_WKPCL(base, wui->group) = BIT(wui->bit);  in npcx_miwu_irq_get_and_clear_pending()
249 		if ((data->both_edge_pins[wui->group] & BIT(wui->bit)) != 0) {  in npcx_miwu_irq_get_and_clear_pending()
250 			npcx_miwu_set_pseudo_both_edge(wui->table, wui->group, wui->bit);  in npcx_miwu_irq_get_and_clear_pending()
252 		k_spin_unlock(&data->lock, key);  in npcx_miwu_irq_get_and_clear_pending()
254 		NPCX_WKPCL(base, wui->group) = BIT(wui->bit);  in npcx_miwu_irq_get_and_clear_pending()
264 	const struct intc_miwu_config *config = miwu_devs[wui->table]->config;  in npcx_miwu_interrupt_configure()
265 	const uint32_t base = config->base;  in npcx_miwu_interrupt_configure()
266 	uint8_t pmask = BIT(wui->bit);  in npcx_miwu_interrupt_configure()
269 	struct intc_miwu_data *data = miwu_devs[wui->table]->data;  in npcx_miwu_interrupt_configure()
273 	/* Disable interrupt of wake-up input source before configuring it */  in npcx_miwu_interrupt_configure()
277 	key = k_spin_lock(&data->lock);  in npcx_miwu_interrupt_configure()
278 	data->both_edge_pins[wui->group] &= ~BIT(wui->bit);  in npcx_miwu_interrupt_configure()
283 		NPCX_WKMOD(base, wui->group) |= pmask;  in npcx_miwu_interrupt_configure()
287 			NPCX_WKEDG(base, wui->group) &= ~pmask;  in npcx_miwu_interrupt_configure()
291 			NPCX_WKEDG(base, wui->group) |= pmask;  in npcx_miwu_interrupt_configure()
294 			ret = -EINVAL;  in npcx_miwu_interrupt_configure()
300 		NPCX_WKMOD(base, wui->group) &= ~pmask;  in npcx_miwu_interrupt_configure()
304 			NPCX_WKAEDG(base, wui->group) &= ~pmask;  in npcx_miwu_interrupt_configure()
305 			NPCX_WKEDG(base, wui->group) |= pmask;  in npcx_miwu_interrupt_configure()
309 			NPCX_WKAEDG(base, wui->group) &= ~pmask;  in npcx_miwu_interrupt_configure()
310 			NPCX_WKEDG(base, wui->group) &= ~pmask;  in npcx_miwu_interrupt_configure()
315 			NPCX_WKAEDG(base, wui->group) &= ~pmask;  in npcx_miwu_interrupt_configure()
316 			data->both_edge_pins[wui->group] |= BIT(wui->bit);  in npcx_miwu_interrupt_configure()
319 			NPCX_WKAEDG(base, wui->group) |= pmask;  in npcx_miwu_interrupt_configure()
323 			ret = -EINVAL;  in npcx_miwu_interrupt_configure()
328 	/* Enable wake-up input sources */  in npcx_miwu_interrupt_configure()
329 	NPCX_WKINEN(base, wui->group) |= pmask;  in npcx_miwu_interrupt_configure()
335 	NPCX_WKPCL(base, wui->group) |= pmask;  in npcx_miwu_interrupt_configure()
338 	if ((data->both_edge_pins[wui->group] & BIT(wui->bit)) != 0) {  in npcx_miwu_interrupt_configure()
339 		npcx_miwu_set_pseudo_both_edge(wui->table, wui->group, wui->bit);  in npcx_miwu_interrupt_configure()
345 	k_spin_unlock(&data->lock, key);  in npcx_miwu_interrupt_configure()
353 	/* Initialize WUI and GPIO settings in unused bits field */  in npcx_miwu_init_gpio_callback()
354 	callback->io_cb.params.wui.table = io_wui->table;  in npcx_miwu_init_gpio_callback()
355 	callback->io_cb.params.wui.bit   = io_wui->bit;  in npcx_miwu_init_gpio_callback()
356 	callback->io_cb.params.gpio_port = port;  in npcx_miwu_init_gpio_callback()
357 	callback->io_cb.params.cb_type = NPCX_MIWU_CALLBACK_GPIO;  in npcx_miwu_init_gpio_callback()
358 	callback->io_cb.params.wui.group = io_wui->group;  in npcx_miwu_init_gpio_callback()
367 	callback->dev_cb.params.wui.table = dev_wui->table;  in npcx_miwu_init_dev_callback()
368 	callback->dev_cb.params.wui.group = dev_wui->group;  in npcx_miwu_init_dev_callback()
369 	callback->dev_cb.params.wui.bit   = dev_wui->bit;  in npcx_miwu_init_dev_callback()
370 	callback->dev_cb.params.source = source;  in npcx_miwu_init_dev_callback()
371 	callback->dev_cb.params.cb_type = NPCX_MIWU_CALLBACK_DEV;  in npcx_miwu_init_dev_callback()
372 	callback->dev_cb.handler = handler;  in npcx_miwu_init_dev_callback()
381 	if (cb->io_cb.params.cb_type == NPCX_MIWU_CALLBACK_GPIO) {  in npcx_miwu_manage_callback()
382 		wui = &cb->io_cb.params.wui;  in npcx_miwu_manage_callback()
384 		wui = &cb->dev_cb.params.wui;  in npcx_miwu_manage_callback()
387 	data = miwu_devs[wui->table]->data;  in npcx_miwu_manage_callback()
388 	cb_list = &data->cb_list_grp[wui->group];  in npcx_miwu_manage_callback()
390 		if (!sys_slist_find_and_remove(cb_list, &cb->node)) {  in npcx_miwu_manage_callback()
392 				return -EINVAL;  in npcx_miwu_manage_callback()
398 		sys_slist_prepend(cb_list, &cb->node);  in npcx_miwu_manage_callback()
415 		int group = 0;                                                 \
420 				intc_miwu_isr_pri(inst, group);                \
421 			group++;                                               \
432 		const struct intc_miwu_config *config = dev->config;           \
433 		const uint32_t base = config->base;                            \
441 		/* Config IRQ and MWIU group directly */                       \