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/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/clock/
Desp32c3_clock.h16 /* Supported CPU Frequencies */
20 /* Supported XTAL Frequencies */
24 /* Supported RTC fast clock frequencies */
28 /* Supported RTC slow clock frequencies */
Desp32s2_clock.h16 /* Supported CPU Frequencies */
23 /* Supported XTAL Frequencies */
26 /* Supported RTC fast clock frequencies */
30 /* Supported RTC slow clock frequencies */
Desp32_clock.h17 /* Supported CPU Frequencies */
24 /* Supported XTAL Frequencies */
30 /* Supported RTC fast clock frequencies */
33 /* Supported RTC slow clock frequencies */
Desp32s3_clock.h16 /* Supported CPU Frequencies */
23 /* Supported XTAL Frequencies */
29 /* Supported RTC fast clock frequencies */
32 /* Supported RTC slow clock frequencies */
/Zephyr-Core-3.5.0/tests/kernel/timer/cycle64/
Dtestcase.yaml10 # As other platforms are added with varying timer frequencies, increase
/Zephyr-Core-3.5.0/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/
Dspi1_pllq_2_d1ppre_4.overlay13 * APB2 and PLL_Q clock frequencies are equal.
/Zephyr-Core-3.5.0/dts/bindings/sensor/
Dti,fdc2x1x.yaml233 1 = divide by 1. Choose for sensor frequencies between
235 2 = divide by 2. Choose for sensor frequencies between 5MHz
239 2 = divide by 2. Choose for sensor frequencies between
/Zephyr-Core-3.5.0/tests/drivers/sdhc/
DREADME.txt16 * Set_IO test: Verify that the SDHC will reject clock frequencies outside of
/Zephyr-Core-3.5.0/soc/arm/arm/beetle/
Dsoc_pll.h50 /* BEETLE PLL Supported Frequencies */
/Zephyr-Core-3.5.0/soc/arm/quicklogic_eos_s3/
Dsoc.h13 /* Available frequencies */
/Zephyr-Core-3.5.0/dts/bindings/spi/
Despressif,esp32-spi.yaml63 possible the use of operating frequencies higher than 20 MHz.
Dmicrochip,xec-qmspi-ldma.yaml85 Allows different frequencies for CS#0 and CS1# devices. This applies
/Zephyr-Core-3.5.0/soc/arm/atmel_sam/sam4s/
Dsoc.c188 * hurt lower clock frequencies. However, a high frequency with too in z_arm_platform_init()
190 * is the safe setting for all of this SoCs usable frequencies. in z_arm_platform_init()
/Zephyr-Core-3.5.0/soc/arm/atmel_sam/sam4e/
Dsoc.c188 * hurt lower clock frequencies. However, a high frequency with too in z_arm_platform_init()
190 * is the safe setting for all of this SoCs usable frequencies. in z_arm_platform_init()
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/reg/
Dmec_pwm.h57 /* PWM input frequencies selected in configuration register. */
/Zephyr-Core-3.5.0/drivers/sensor/bmi08x/
Dbmi08x.c12 * Output data rate map with allowed frequencies:
/Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/sifive-freedom/
Dfe310_clock.c21 * peripheral clock). This code supports the following frequencies: in fe310_clock_init()
/Zephyr-Core-3.5.0/soc/riscv/espressif_esp32/esp32c3/
DKconfig.soc70 startup, and approximate clock frequencies will be assumed:
/Zephyr-Core-3.5.0/tests/bluetooth/tester/src/btp/
Dbtp_bap.h124 uint16_t frequencies; member
/Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/telink_b91/
Dsoc.c16 /* List of supported CCLK frequencies */
/Zephyr-Core-3.5.0/doc/build/dts/
Ddt-vs-kconfig.rst13 Examples include peripherals on a board, boot-time clock frequencies,
/Zephyr-Core-3.5.0/drivers/sensor/bmg160/
Dbmg160.c114 /* Allowed sampling frequencies, in Hz */
175 * The sampling frequencies values start at 1, i.e. a in bmg160_attr_set()
/Zephyr-Core-3.5.0/dts/bindings/clock/
Dst,stm32-rcc.yaml128 On some parts, it could be required to set up highest core frequencies
/Zephyr-Core-3.5.0/drivers/mipi_dsi/
Ddsi_mcux.c114 * frequencies in dsi_mcux_best_clock()
136 /* SKIP frequencies less than target frequency. in dsi_mcux_best_clock()
/Zephyr-Core-3.5.0/tests/drivers/sdhc/src/
Dmain.c52 /* Verify that driver rejects frequencies outside of claimed range */

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