1description: ESP32 SPI
2
3compatible: "espressif,esp32-spi"
4
5include: [spi-controller.yaml, pinctrl-device.yaml]
6
7properties:
8  reg:
9    required: true
10
11  pinctrl-0:
12    required: true
13
14  pinctrl-names:
15    required: true
16
17  half-duplex:
18    type: boolean
19    description: |
20      Enable half-duplex communication mode.
21
22      Transmit data before receiving it, instead of simultaneously
23
24  dummy-comp:
25    type: boolean
26    description: Enable dummy SPI compensation cycles
27
28  sio:
29    type: boolean
30    description: |
31      Enable 3-wire mode
32
33      Use MOSI for both sending and receiving data
34
35  dma-enabled:
36    type: boolean
37    description: Enable SPI DMA support
38
39  dma-clk:
40    type: int
41    description: DMA clock source
42
43  dma-host:
44    type: int
45    description: DMA Host - 0 -> SPI2, 1 -> SPI3
46
47  clk-as-cs:
48    type: boolean
49    description: |
50      Support to toggle the CS while the clock toggles
51
52      Output clock on CS line if CS is active
53
54  positive-cs:
55    type: boolean
56    description: Make CS positive during a transaction instead of negative
57
58  use-iomux:
59    type: boolean
60    description: |
61      Some pins are allowed to bypass the GPIO Matrix and use the IO_MUX
62      routing mechanism instead, this avoids extra routing latency and makes
63      possible the use of operating frequencies higher than 20 MHz.
64
65      Refer to SoC's Technical Reference Manual to check which pins are
66      allowed to use this routing path.
67
68  cs-setup-time:
69    type: int
70    description: |
71      Chip select setup time setting, see TRF for SOC for details of
72      timing applied.
73
74  cs-hold-time:
75    type: int
76    description: |
77      Chip select hold time setting, see TRF for SOC for details of
78      timing applied.
79
80  line-idle-low:
81    type: boolean
82    description: |
83      Default MISO and MOSI pins GPIO level when idle. Defaults to high by default.
84