1 /* 2 * Copyright (c) 2020 Antmicro <www.antmicro.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _SOC__H_ 8 #define _SOC__H_ 9 10 #include <zephyr/sys/util.h> 11 #include <eoss3_dev.h> 12 13 /* Available frequencies */ 14 #define HSOSC_1MHZ 1024000 15 #define HSOSC_2MHZ (2*HSOSC_1MHZ) 16 #define HSOSC_3MHZ (3*HSOSC_1MHZ) 17 #define HSOSC_4MHZ (4*HSOSC_1MHZ) 18 #define HSOSC_5MHZ (5*HSOSC_1MHZ) 19 #define HSOSC_6MHZ (6*HSOSC_1MHZ) 20 #define HSOSC_8MHZ (8*HSOSC_1MHZ) 21 #define HSOSC_9MHZ (9*HSOSC_1MHZ) 22 #define HSOSC_10MHZ (10*HSOSC_1MHZ) 23 #define HSOSC_12MHZ (12*HSOSC_1MHZ) 24 #define HSOSC_15MHZ (15*HSOSC_1MHZ) 25 #define HSOSC_16MHZ (16*HSOSC_1MHZ) 26 #define HSOSC_18MHZ (18*HSOSC_1MHZ) 27 #define HSOSC_20MHZ (20*HSOSC_1MHZ) 28 #define HSOSC_21MHZ (21*HSOSC_1MHZ) 29 #define HSOSC_24MHZ (24*HSOSC_1MHZ) 30 #define HSOSC_27MHZ (27*HSOSC_1MHZ) 31 #define HSOSC_30MHZ (30*HSOSC_1MHZ) 32 #define HSOSC_32MHZ (32*HSOSC_1MHZ) 33 #define HSOSC_35MHZ (35*HSOSC_1MHZ) 34 #define HSOSC_36MHZ (36*HSOSC_1MHZ) 35 #define HSOSC_40MHZ (40*HSOSC_1MHZ) 36 #define HSOSC_45MHZ (45*HSOSC_1MHZ) 37 #define HSOSC_48MHZ (48*HSOSC_1MHZ) 38 #define HSOSC_54MHZ (54*HSOSC_1MHZ) 39 #define HSOSC_60MHZ (60*HSOSC_1MHZ) 40 #define HSOSC_64MHZ (64*HSOSC_1MHZ) 41 #define HSOSC_70MHZ (70*HSOSC_1MHZ) 42 #define HSOSC_72MHZ (72*HSOSC_1MHZ) 43 #define HSOSC_80MHZ (80*HSOSC_1MHZ) 44 45 #define OSC_CLK_LOCKED() (AIP->OSC_STA_0 & 0x1) 46 #define OSC_SET_FREQ_INC(FREQ) (AIP->OSC_CTRL_1 = ((FREQ / 32768) - 3) & 0xFFF) 47 #define OSC_GET_FREQ_INC() (((AIP->OSC_CTRL_1 & 0xFFF) + 3) * 32768) 48 49 void eos_s3_lock_enable(void); 50 void eos_s3_lock_disable(void); 51 52 #endif /* _SOC__H_ */ 53
