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/Zephyr-latest/drivers/i2c/
Di2c_xilinx_axi.h1 /* SPDX-License-Identifier: Apache-2.0 */
16 REG_GIE = 0x01C, /* Global Interrupt Enable */
18 REG_IER = 0x028, /* Interrupt Enable */
22 REG_TX_FIFO = 0x108, /* Transmit FIFO */
23 REG_RX_FIFO = 0x10C, /* Receive FIFO */
25 REG_TX_FIFO_OCY = 0x114, /* Transmit FIFO Occupancy */
26 REG_RX_FIFO_OCY = 0x118, /* Receive FIFO Occupancy */
28 REG_RX_FIFO_PIRQ = 0x120, /* Receive FIFO Programmable Depth Interrupt */
41 /* Global Interrupt Enable */
46 /* Interrupt Status/Interrupt Enable */
[all …]
DKconfig.it8xxx22 # SPDX-License-Identifier: Apache-2.0
10 Enable I2C support on it8xxx2_evb.
17 bool "IT8XXX2 I2C FIFO mode"
20 This is an option to enable FIFO mode which can reduce
23 The I2C controller supports two 32-bytes FIFOs,
25 I2C FIFO mode of it8xxx2 can support I2C APIs including:
36 This option can enable the enhance I2C
46 This is an option to enable command queue mode which can
/Zephyr-latest/drivers/serial/
DKconfig.esp321 # SPDX-License-Identifier: Apache-2.0
13 Enable the ESP32 UART.
16 bool "ESP32 built-in USB serial driver"
22 Enable the built-in USB serial interface present in some Espressif
23 MCUs like ESP32-Cx.
26 (USB_SERIAL_JTAG), which acts as a CDC-ACM interface towards the
32 hex "ESP32 UART TX FIFO Threshold"
37 Configure the TX FIFO threshold for ESP32 UART driver.
40 hex "ESP32 UART RX FIFO Threshold"
45 Configure the RX FIFO threshold for ESP32 UART driver.
DKconfig.renesas_ra82 # SPDX-License-Identifier: Apache-2.0
15 Enable Renesas RA SCI_B UART Driver.
20 bool "RA SCI_B UART FIFO usage enable"
24 Enable RA SCI_B FIFO
DKconfig.renesas_ra3 # SPDX-License-Identifier: Apache-2.0
13 Enable Renesas RA series UART driver.
26 Enable Renesas RA SCI UART Driver.
31 bool "RA SCI UART FIFO usage enable"
34 Enable RA SCI FIFO
Duart_apbuart.c2 * Copyright (c) 2019-2020 Cobham Gaisler AB
4 * SPDX-License-Identifier: Apache-2.0
17 * ------ | ------ | ----------------------------------------
22 * 0x0010 | debug | UART FIFO debug register
29 * ------ | ------ | ----------------------------------------
30 * 7-0 | data | Holding register or FIFO
37 * ------ | ------ | ----------------------------------------
38 * 31-26 | RCNT | Receiver FIFO count
39 * 25-20 | TCNT | Transmitter FIFO count
40 * 10 | RF | Receiver FIFO full
[all …]
DKconfig.ns165501 # SPDX-License-Identifier: Apache-2.0
9 select PINCTRL if $(dt_compat_any_has_prop,$(DT_COMPAT_NS16550),pinctrl-0)
48 bool "UART 16550 (16-bytes FIFO)"
50 This enables support for 16-bytes FIFO if UART controller is 16550.
53 bool "UART 16750 (64-bytes FIFO and auto flow control)"
55 This enables support for 64-bytes FIFO and automatic hardware
59 bool "UART 16950 (128-bytes FIFO and auto flow control)"
61 This enables support for 128-bytes FIFO and automatic hardware flow control.
87 Enable IT8XXX2 specific baud rate configuration.
88 This applies to high-speed baud rate configuration.
[all …]
Duart_pl011_registers.h6 * SPDX-License-Identifier: Apache-2.0
45 #define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
48 #define PL011_FR_CTS BIT(0) /* clear to send - inverted */
49 #define PL011_FR_DSR BIT(1) /* data set ready - inverted */
50 #define PL011_FR_DCD BIT(2) /* data carrier detect - inverted */
52 #define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
53 #define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
54 #define PL011_FR_RXFF BIT(6) /* receive FIFO full */
55 #define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
56 #define PL011_FR_RI BIT(8) /* ring indicator - inverted */
[all …]
Duart_rcar.c4 * SPDX-License-Identifier: Apache-2.0
46 #define SCFTDR 0x0c /* Transmit FIFO Data Register */
48 #define SCFRDR 0x14 /* Receive FIFO Data Register */
49 #define SCFCR 0x18 /* FIFO Control Register */
50 #define SCFDR 0x1c /* FIFO Data Count Register */
59 #define SCSMR_CHR BIT(6) /* 7-bit Character Length */
60 #define SCSMR_PE BIT(5) /* Parity Enable */
67 #define SCSCR_TEIE BIT(11) /* Transmit End Interrupt Enable */
68 #define SCSCR_TIE BIT(7) /* Transmit Interrupt Enable */
69 #define SCSCR_RIE BIT(6) /* Receive Interrupt Enable */
[all …]
/Zephyr-latest/dts/bindings/serial/
Dst,stm32-uart-base.yaml2 # SPDX-License-Identifier: Apache-2.0
5 description: STM32 UART-BASE
8 - name: uart-controller.yaml
9 property-blocklist:
10 - clock-frequency
11 - name: pinctrl-device.yaml
12 - name: reset-device.yaml
13 - name: uart-controller-pin-inversion.yaml
28 single-wire:
31 Enable the single wire half-duplex communication.
[all …]
/Zephyr-latest/dts/bindings/spi/
Dnxp,dspi.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: ["spi-controller.yaml", "pinctrl-device.yaml"]
20 pcs-sck-delay:
26 sck-pcs-delay:
32 transfer-delay:
38 pinctrl-0:
41 nxp,rx-tx-chn-share:
48 ctar register selection range form 0-1 for master mode, 0 for slave mode
50 sample-point:
56 continuous-sck:
[all …]
Dst,stm32h7-spi.yaml2 # SPDX-License-Identifier: Apache-2.0
9 presence of a dedicated interrupt enable register (IER).
12 compatible: "st,stm32h7-spi"
14 include: st,stm32-spi-common.yaml
17 midi-clock:
21 (Master Inter-Data Idleness) minimum clock inserted
24 mssi-clock:
31 fifo-enable:
33 description: Enable the SPI FIFO usage for performance improvement.
/Zephyr-latest/samples/boards/st/power_mgmt/serial_wakeup/boards/
Dnucleo_wl55jc.overlay4 * SPDX-License-Identifier: Apache-2.0
14 current-speed = <9600>;
16 /* Enable as wakeup source */
17 wakeup-source;
19 /* Enable FIFO to avoid losing chars on device wakeup */
20 fifo-enable;
Dnucleo_h563zi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 wakeup-source;
15 /* Enable FIFO to avoid losing chars on device wakeup */
16 fifo-enable;
22 pinctrl-1 = <&analog_pd8 &analog_pd9>;
23 pinctrl-names = "default", "sleep";
Db_u585i_iot02a.overlay4 * SPDX-License-Identifier: Apache-2.0
12 cpu-power-states = <&stop0 &stop1>;
21 wakeup-source;
23 /* Enable FIFO to avoid losing chars on device wakeup */
24 fifo-enable;
30 pinctrl-1 = <&analog_pa9 &analog_pa10>;
31 pinctrl-names = "default", "sleep";
Dnucleo_wb55rg.overlay5 * SPDX-License-Identifier: Apache-2.0
13 cpu-power-states = <&stop0 &stop1>;
22 wakeup-source;
24 /* Enable FIFO to avoid losing chars on device wakeup */
25 fifo-enable;
31 pinctrl-1 = <&analog_pb6 &analog_pb7>;
32 pinctrl-names = "default", "sleep";
/Zephyr-latest/tests/drivers/uart/uart_basic_api/src/
Dtest_uart_fifo.c4 * SPDX-License-Identifier: Apache-2.0
11 * @brief TestPurpose: verify UART works well in fifo mode
13 * - Test Steps
14 * - FIFO Output:
15 * -# Set UART IRQ callback using uart_irq_callback_set().
16 * -# Enable UART TX IRQ using uart_irq_tx_enable().
17 * -# Output the prepared data using uart_fifo_fill().
18 * -# Disable UART TX IRQ using uart_irq_tx_disable().
19 * -# Compare the number of characters sent out with the
21 * - FIFO Input:
[all …]
/Zephyr-latest/drivers/entropy/
Dentropy_gecko_trng.c4 * SPDX-License-Identifier: Apache-2.0
17 * Select the correct Crypto ACC FIFO memory base address.
20 * ACC RNGOUT FIFO memory base address, like it does for register address definitions.
23 * appropriate FIFO memory base address.
35 #define S2_FIFO_LEVEL (CRYPTOACC_RNGCTRL->FIFOLEVEL)
36 #define S2_CTRL (CRYPTOACC_RNGCTRL->RNGCTRL)
39 #define S2_FIFO_LEVEL (CRYPTOACC->NDRNG_FIFOLEVEL)
40 #define S2_CTRL (CRYPTOACC->NDRNG_CONTROL)
55 *data++ = TRNG0->FIFO; in entropy_gecko_trng_read()
56 len -= 4; in entropy_gecko_trng_read()
[all …]
/Zephyr-latest/drivers/i3c/
DKconfig.stm323 # SPDX-License-Identifier: Apache-2.0
6 module-str = i3c_stm32
15 Enable support for I3C on STM32 microcontrollers.
26 int "Status FIFO and control FIFO heap"
31 storing status FIFO and control FIFO words which will be used by the DMA.
/Zephyr-latest/soc/intel/intel_adsp/ace/include/
Ddmic_regs.h1 /* SPDX-License-Identifier: Apache-2.0 */
36 /* Interrupt on New Timestamp Enable */
42 /* Capture Link Select - select which link wall clock to time stamp. */
45 /* Hammock Harbor Time Stamp Enable */
68 /* Common FIFO channels register (primary & secondary) (0000 - 0FFF)
75 /* Status Register for FIFO interface */
78 /* Data read/Write port for FIFO */
82 * (crossed out) 0010h LOCAL_TSC0 64-bit Wall Clock timestamp
83 * (crossed out) 0018h LOCAL_SAMPLE0 64-bit Sample Count
84 * 001Ch - 00FFh Reserved space for extensions
[all …]
/Zephyr-latest/soc/intel/intel_adsp/cavs/include/cavs25/
Ddmic_regs.h1 /* SPDX-License-Identifier: Apache-2.0 */
36 /* Interrupt on New Timestamp Enable */
42 /* Hammock Harbor Time Stamp Enable */
65 /* Common FIFO channels register (primary & secondary) (0000 - 0FFF)
72 /* Status Register for FIFO interface */
75 /* Data read/Write port for FIFO */
79 * (crossed out) 0010h LOCAL_TSC0 64-bit Wall Clock timestamp
80 * (crossed out) 0018h LOCAL_SAMPLE0 64-bit Sample Count
81 * 001Ch - 00FFh Reserved space for extensions
151 /* Threshold Interrupt Enable */
[all …]
/Zephyr-latest/include/zephyr/sd/
Dsdio.h4 * SPDX-License-Identifier: Apache-2.0
30 * @param card: SD card to enable function on
33 * @retval -EIO: I/O error
39 * @brief Enable SDIO function
43 * @param func: function to enable
45 * @retval -ETIMEDOUT: card I/O timed out
46 * @retval -EIO: I/O error
58 * @retval -EINVAL: unsupported/invalid block size
59 * @retval -EIO: I/O error
71 * @retval -EBUSY: card is busy with another request
[all …]
/Zephyr-latest/drivers/can/
DKconfig.xmc4xxx3 # SPDX-License-Identifier: Apache-2.0
11 Enable Infineon XMC4xxx CAN Driver
24 int "Number of CAN messages allocated to each RX FIFO"
28 Defines the number of CAN messages in each RX FIFO. A separate RX FIFO
DKconfig.nxp_s321 # Copyright 2022-2024 NXP
2 # SPDX-License-Identifier: Apache-2.0
11 Enable support for NXP S32 CANXL driver.
15 bool "NXP S32 CANXL uses RX FIFO"
18 If this is enabled, NXP S32 CANXL uses RX FIFO.
/Zephyr-latest/drivers/dai/nxp/esai/
Desai.h4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/dai/esai.h>
32 /* used to fetch the depth of the FIFO. If the "fifo-depth" property is
33 * not specified, the FIFO depth that will be reported to the upper layers
34 * will be 128 * 4 (which is the maximum value, or, well, the actual FIFO
40 /* used to fetch the TX FIFO watermark value. If the "tx-fifo-watermark"
41 * property is not specified, this will be set to half of the FIFO depth.
46 /* used to fetch the RX FIFO watermark value. If the "rx-fifo-watermark"
47 * property is not specified, this will be set to half of the FIFO depth.
61 /* used to fetch the word width. If the "word-width" property is not specified,
[all …]

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