Lines Matching +full:fifo +full:- +full:enable
6 * SPDX-License-Identifier: Apache-2.0
45 #define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
48 #define PL011_FR_CTS BIT(0) /* clear to send - inverted */
49 #define PL011_FR_DSR BIT(1) /* data set ready - inverted */
50 #define PL011_FR_DCD BIT(2) /* data carrier detect - inverted */
52 #define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
53 #define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
54 #define PL011_FR_RXFF BIT(6) /* receive FIFO full */
55 #define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
56 #define PL011_FR_RI BIT(8) /* ring indicator - inverted */
76 #define PL011_LCRH_PEN BIT(1) /* enable parity */
79 #define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
84 #define PL011_LCRH_WLEN_SIZE(x) (x - 5)
95 #define PL011_CR_UARTEN BIT(0) /* enable uart operations */
96 #define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
98 #define PL011_CR_LBE BIT(7) /* loop back enable */
99 #define PL011_CR_TXE BIT(8) /* transmit enable */
100 #define PL011_CR_RXE BIT(9) /* receive enable */
105 #define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable */
106 #define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable */
108 /* PL011 Control Register - vendor-specific fields */
109 #define PL011_CR_AMBIQ_CLKEN BIT(3) /* clock enable */
118 /* PL011 Interrupt Fifo Level Select Register */