# Copyright (c) 2022, Linaro Limited
# SPDX-License-Identifier: Apache-2.0

description: |
        STM32H7 SPI controller
        This compatible stands for all SPI hardware blocks matching the
        version available in STM32H7 SoCs.
        This version of STM32 SPI hardware block could be identified by the
        presence of a dedicated interrupt enable register (IER).
        For instance, but not limited  to: STM32MP1, STM32U5

compatible: "st,stm32h7-spi"

include: st,stm32-spi-common.yaml

properties:
  midi-clock:
    type: int
    default: 0
    description: |
      (Master Inter-Data Idleness) minimum clock inserted
      between two consecutive data frames.

  mssi-clock:
    type: int
    default: 0
    description: |
      (Master SS Idleness) minimum clock inserted between
      start and first data transaction.

  fifo-enable:
    type: boolean
    description: Enable the SPI FIFO usage for performance improvement.
