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/Zephyr-latest/dts/bindings/serial/
Daltr,jtag-uart.yaml3 compatible: "altr,jtag-uart"
5 include: uart-controller.yaml
11 write-fifo-depth:
15 Buffer size of transmit fifo. This used to implement irq_tx_complete.
16 Must be same as Write FIFO: Buffer depth (bytes) in platform designer.
/Zephyr-latest/dts/bindings/dai/
Dnxp,dai-esai.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,dai-esai"
13 dai-index:
21 tx-fifo-watermark:
25 FIFO. This value needs to be in FIFO words (NOT BYTES). This
28 the TX FIFO watermark will be set to DEFAULT_FIFO_DEPTH / 2.
29 rx-fifo-watermark:
33 FIFO. This values needs to be in FIFO words (NOT BYTES). This
36 the RX FIFO watermark will be set to DEFAULT_FIFO_DEPTH / 2.
37 fifo-depth:
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Dnxp,dai-sai.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,dai-sai"
8 include: [base.yaml, pinctrl-device.yaml]
13 mclk-is-output:
21 rx-fifo-watermark:
25 FIFO. This value needs to be in FIFO words (NOT BYTES). This
28 tx-fifo-watermark:
32 FIFO. This value needs to be in FIFO words (NOT BYTES). This
37 fifo-depth:
40 Use this property to set the FIFO depth that will be reported
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/Zephyr-latest/dts/bindings/spi/
Dsnps,designware-spi.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "snps,designware-spi"
9 include: [spi-controller.yaml, pinctrl-device.yaml]
18 aux-reg:
24 fifo-depth:
27 RX/TX FIFO depth. Corresponds to the SSI_TX_FIFO_DEPTH
29 Serial Interface. Depth ranges from 2-256.
31 serial-target:
38 max-xfer-size:
45 - 16
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Dintel,penwell-spi.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "intel,penwell-spi"
9 include: [spi-controller.yaml, pcie-device.yaml]
15 cs-gpios:
18 pw,cs-mode:
27 pw,cs-output:
37 pw,fifo-depth:
/Zephyr-latest/dts/arc/synopsys/
Demsdp.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 //#include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
26 intc: arcv2-intc {
27 compatible = "snps,arcv2-intc";
28 interrupt-controller;
29 #interrupt-cells = <2>;
33 compatible = "snps,arc-timer";
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Darc_hs4xd.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
43 intc: arcv2-intc {
44 compatible = "snps,arcv2-intc";
45 interrupt-controller;
46 #interrupt-cells = <2>;
50 idu_intc: idu-interrupt-controller {
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Darc_hsdk.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
43 intc: arcv2-intc {
44 compatible = "snps,arcv2-intc";
45 interrupt-controller;
46 #interrupt-cells = <2>;
50 idu_intc: idu-interrupt-controller {
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Demsk.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
25 intc: arcv2-intc {
26 compatible = "snps,arcv2-intc";
27 interrupt-controller;
28 #interrupt-cells = <2>;
32 compatible = "snps,arc-timer";
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/Zephyr-latest/soc/intel/intel_adsp/cavs/include/cavs25/
Ddmic_regs.h1 /* SPDX-License-Identifier: Apache-2.0 */
65 /* Common FIFO channels register (primary & secondary) (0000 - 0FFF)
72 /* Status Register for FIFO interface */
75 /* Data read/Write port for FIFO */
79 * (crossed out) 0010h LOCAL_TSC0 64-bit Wall Clock timestamp
80 * (crossed out) 0018h LOCAL_SAMPLE0 64-bit Sample Count
81 * 001Ch - 00FFh Reserved space for extensions
149 #define OUTCONTROL_BFTH_MAX 4 /* Max depth 16 */
157 /* FIFO Initialize (FINIT): The software will set this bit to immediately clear FIFO pointers. */
163 /* Burst FIFO Threshold */
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/Zephyr-latest/drivers/dai/nxp/esai/
Desai.h4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/dai/esai.h>
32 /* used to fetch the depth of the FIFO. If the "fifo-depth" property is
33 * not specified, the FIFO depth that will be reported to the upper layers
34 * will be 128 * 4 (which is the maximum value, or, well, the actual FIFO
35 * depth)
40 /* used to fetch the TX FIFO watermark value. If the "tx-fifo-watermark"
41 * property is not specified, this will be set to half of the FIFO depth.
46 /* used to fetch the RX FIFO watermark value. If the "rx-fifo-watermark"
47 * property is not specified, this will be set to half of the FIFO depth.
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/Zephyr-latest/dts/bindings/dma/
Dgd,gd32-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
5 GD32 DMA controller with FIFO
12 - bit 6-7: Direction (see dma.h)
13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
18 - bit 9: Peripheral address increase
19 - 0x0: no address increment between transfers
20 - 0x1: increment address between transfers
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/Zephyr-latest/soc/intel/intel_adsp/ace/include/
Ddmic_regs.h1 /* SPDX-License-Identifier: Apache-2.0 */
42 /* Capture Link Select - select which link wall clock to time stamp. */
68 /* Common FIFO channels register (primary & secondary) (0000 - 0FFF)
75 /* Status Register for FIFO interface */
78 /* Data read/Write port for FIFO */
82 * (crossed out) 0010h LOCAL_TSC0 64-bit Wall Clock timestamp
83 * (crossed out) 0018h LOCAL_SAMPLE0 64-bit Sample Count
84 * 001Ch - 00FFh Reserved space for extensions
152 #define OUTCONTROL_BFTH_MAX 4 /* Max depth 16 */
160 /* FIFO Initialize (FINIT): The software will set this bit to immediately clear FIFO pointers. */
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/Zephyr-latest/drivers/dai/intel/ssp/
Dssp.h4 * SPDX-License-Identifier: Apache-2.0
30 #include "dai-params-intel-ipc3.h"
31 #include "dai-params-intel-ipc4.h"
34 (((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL) << (b_lo))
37 (((x) & ((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL)) << (b_lo))
46 #define DAI_INTEL_SSP_MAX_FREQ_INDEX (DAI_INTEL_SSP_NUM_FREQ - 1)
49 /* the SSP port fifo depth */
52 /* the watermark for the SSP fifo depth setting */
80 /** \brief BCLKs can be driven by multiple sources - M/N or XTAL directly.
124 uint32_t depth; member
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/Zephyr-latest/drivers/i2c/
Di2c_xilinx_axi.h1 /* SPDX-License-Identifier: Apache-2.0 */
22 REG_TX_FIFO = 0x108, /* Transmit FIFO */
23 REG_RX_FIFO = 0x10C, /* Receive FIFO */
25 REG_TX_FIFO_OCY = 0x114, /* Transmit FIFO Occupancy */
26 REG_RX_FIFO_OCY = 0x118, /* Receive FIFO Occupancy */
28 REG_RX_FIFO_PIRQ = 0x120, /* Receive FIFO Programmable Depth Interrupt */
48 ISR_TX_HALF_EMPTY = BIT(7), /* Transmit FIFO Half Empty */
52 ISR_RX_FIFO_FULL = BIT(3), /* Receive FIFO Full */
53 ISR_TX_FIFO_EMPTY = BIT(2), /* Transmit FIFO Empty */
70 CR_TX_FIFO_RST = BIT(1), /* Transmit FIFO Reset */
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/Zephyr-latest/doc/kernel/services/data_passing/
Dfifos.rst6 A :dfn:`FIFO` is a kernel object that implements a traditional
7 first in, first out (FIFO) queue, allowing threads and ISRs
12 :depth: 2
17 Any number of FIFOs can be defined (limited only by available RAM). Each FIFO is
20 A FIFO has the following key properties:
25 A FIFO must be initialized before it can be used. This sets its queue to empty.
27 FIFO data items must be aligned on a word boundary, as the kernel reserves
36 FIFO data items are restricted to single active instance across all FIFO
37 data queues. Any attempt to re-add a FIFO data item to a queue before
41 A data item may be **added** to a FIFO by a thread or an ISR.
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/Zephyr-latest/drivers/serial/
Duart_cc32xx.c2 * Copyright (c) 2016-2017, Texas Instruments Incorporated
4 * SPDX-License-Identifier: Apache-2.0
48 * CC32XX UART has a configurable FIFO length, from 1 to 8 characters.
50 * a RX FIFO depth of one: meaning, one interrupt == one character received.
52 * and at depth 1.
56 const struct uart_cc32xx_dev_config *config = dev->config; in uart_cc32xx_init()
57 const struct uart_cc32xx_dev_data_t *data = dev->data; in uart_cc32xx_init()
60 MAP_PRCMPeripheralClkEnable(data->prcm, in uart_cc32xx_init()
63 MAP_PRCMPeripheralReset(data->prcm); in uart_cc32xx_init()
65 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in uart_cc32xx_init()
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/Zephyr-latest/dts/x86/intel/
Dalder_lake.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "intel,alder-lake", "intel,x86_64";
22 d-cache-line-size = <64>;
28 compatible = "intel,alder-lake";
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Draptor_lake_p.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/pcie/pcie.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "intel,raptor-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 interrupt-controller;
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Draptor_lake_s.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/pcie/pcie.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,raptor-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
[all …]
/Zephyr-latest/dts/arm/intel_socfpga_std/
Dsocfpga.dtsi2 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
28 compatible = "arm,cortex-a9";
31 /* next-level-cache = <&L2>; */ /*cache driver not available yet */
34 compatible = "arm,cortex-a9";
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/Zephyr-latest/drivers/i3c/
Di3c_cdns.c4 * SPDX-License-Identifier: Apache-2.0
472 /* Target T_LOW period in open-drain mode. */
482 /* command response fifo threshold */
484 /* command tx fifo threshold - unused */
486 /* in-band-interrupt data fifo threshold - unused */
488 /* in-band-interrupt response queue threshold */
490 /* tx data threshold - unused */
504 /* The maxiumum command queue depth. */
506 /* The maxiumum command response queue depth. */
508 /* The maximum RX FIFO depth. */
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/Zephyr-latest/drivers/dai/intel/dmic/
Ddmic.h4 * SPDX-License-Identifier: Apache-2.0
29 #define DMIC_HW_CIC_SHIFT_MIN -8
53 #define DMIC_HW_FIR_COEF_MAX ((1 << (DMIC_HW_BITS_FIR_COEF - 1)) - 1)
54 #define DMIC_HW_FIR_COEF_Q (DMIC_HW_BITS_FIR_COEF - 1)
60 #define DMIC_HW_FIR_GAIN_MAX ((1 << (DMIC_HW_BITS_FIR_GAIN - 1)) - 1)
67 * decibels, set to -90 dB.
72 * dy = y48 - y16; dx = 48000 - 16000;
74 * offs = round(y16 - coef/2^15 * 16000)
78 #define LOGRAMP_START_DB Q_CONVERT_FLOAT(-90, DB2LIN_FIXED_INPUT_QY)
79 #define LOGRAMP_TIME_COEF_Q15 -102 /* coef = dy/dx */
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/Zephyr-latest/doc/kernel/services/
Dpolling.rst11 :depth: 2
25 - a semaphore becomes available
26 - a kernel FIFO contains data ready to be retrieved
27 - a kernel message queue contains data ready to be retrieved
28 - a kernel pipe contains data ready to be retrieved
29 - a poll signal is raised
48 Apart from the kernel objects, there is also a **poll signal** pseudo-object
54 :c:func:`k_poll` was called, or due to the preemptive multi-threading
91 .. code-block:: c
110 .. code-block:: c
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/Zephyr-latest/drivers/usb/udc/
Dudc_dwc2.c4 * SPDX-License-Identifier: Apache-2.0
44 /* Minimum RX FIFO size in 32-bit words considering the largest used OUT packet
49 /* Default Rx FIFO size in 32-bit words calculated to support High-Speed with:
57 /* TX FIFO0 depth in 32-bit words (used by control IN endpoint)
63 /* Get Data FIFO access register */
105 /* Transfer triggers (IN on bits 0-15, OUT on bits 16-31) */
107 /* Finished transactions (IN on bits 0-15, OUT on bits 16-31) */
143 const struct udc_dwc2_config *const config = dev->config; in dwc2_init_pinctrl()
144 const struct pinctrl_dev_config *const pcfg = config->pcfg; in dwc2_init_pinctrl()
172 const struct udc_dwc2_config *const config = dev->config; in dwc2_get_base()
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