4  * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/dai/esai.h>
32 /* used to fetch the depth of the FIFO. If the "fifo-depth" property is
33  * not specified, the FIFO depth that will be reported to the upper layers
34  * will be 128 * 4 (which is the maximum value, or, well, the actual FIFO
35  * depth)
40 /* used to fetch the TX FIFO watermark value. If the "tx-fifo-watermark"
41  * property is not specified, this will be set to half of the FIFO depth.
46 /* used to fetch the RX FIFO watermark value. If the "rx-fifo-watermark"
47  * property is not specified, this will be set to half of the FIFO depth.
61 /* used to fetch the word width. If the "word-width" property is not specified,
76 #define _ESAI_SLOT_WORD_WIDTH_IS_VALID(width) (!(((width) - 8) % 4))
88 	((w) < 24 ? ((s) - (w) + (((w) - 8) / 4)) : ((s) < 32 ? 0x1e : 0x1f))
94 #define ESAI_WORD_ALIGNMENT(word_width) ((32 - (word_width)) / 4)
106 /* used to fetch the mask for setting TX/RX FIFO usage. By FIFO usage
108  * FIFO (i.e: the FIFO that's common to all transmitters/receivers).
133 /* used to fetch the base address of the TX FIFO */
135 	POINTER_TO_UINT(&(UINT_TO_ESAI(DT_INST_REG_ADDR(inst))->ETDR))
137 /* used to fetch the base address of the RX FIFO */
139 	POINTER_TO_UINT(&(UINT_TO_ESAI(DT_INST_REG_ADDR(inst))->ERDR))
153 	(((data)->pcrc & BIT(which)) && ((data->prrc) & BIT(which)))
195 	/* clock-related data */
200 	/* TDM-related data */
212 	/* controls the divison value of HCLK (i.e: TPM0-TPM7) */
215 	 * BCLK consumers (i.e: TFP0-TFP3)
223 	/* HCLK direction - input or output */
225 	/* HCLK source - EXTAL or IPG clock */
227 	/* HCLK polarity - LOW or HIGH */
230 	/* BCLK direction - input or output */
232 	/* BCLK polarity - LOW or HIGH */
235 	/* FSYNC direction - input or output */
237 	/* FSYNC polarity - LOW or HIGH */
240 	/* should FSYNC be bit-wide or word-wide? */
244 	 * bit - see TCR's PADC bit for more info.
252 	/* FSYNC divison value - for network mode this is
253 	 * the same as the number of slots - 1.
257 	/* slot format - see TCR's TSWS or RCR's RSWS */
259 	/* mode - network or normal
268 	 * word is left-aligned, otherwise it will be right-aligned.
276 	 * slots should be High-Z or data.
279 	/* controls the alignment of data written to FIFO.
292 	for (i = 0; i < cfg->clock_cfg_size; i += 2) {  in esai_parse_clock_config()
293 		crt_clock = cfg->clock_cfg[i];  in esai_parse_clock_config()
294 		crt_dir = cfg->clock_cfg[i + 1];  in esai_parse_clock_config()
299 			return -EINVAL;  in esai_parse_clock_config()
304 			return -EINVAL;  in esai_parse_clock_config()
309 			tx_cfg->hclk_dir = crt_dir;  in esai_parse_clock_config()
312 			rx_cfg->hclk_dir = crt_dir;  in esai_parse_clock_config()
315 			tx_cfg->bclk_dir = crt_dir;  in esai_parse_clock_config()
318 			rx_cfg->bclk_dir = crt_dir;  in esai_parse_clock_config()
321 			tx_cfg->fsync_dir = crt_dir;  in esai_parse_clock_config()
324 			rx_cfg->fsync_dir = crt_dir;  in esai_parse_clock_config()
339 	data->pcrc = ESAI_PCRC_PC_MASK;  in esai_parse_pinmodes()
340 	data->prrc = ESAI_PRRC_PDC_MASK;  in esai_parse_pinmodes()
342 	for (i = 0; i < cfg->pinmodes_size; i += 2) {  in esai_parse_pinmodes()
343 		pin = cfg->pinmodes[i];  in esai_parse_pinmodes()
344 		pin_mode = cfg->pinmodes[i + 1];  in esai_parse_pinmodes()
347 			return -EINVAL;  in esai_parse_pinmodes()
352 			data->pcrc &= ~BIT(pin);  in esai_parse_pinmodes()
353 			data->prrc &= ~BIT(pin);  in esai_parse_pinmodes()
356 			data->pcrc &= ~BIT(pin);  in esai_parse_pinmodes()
359 			data->prrc &= ~BIT(pin);  in esai_parse_pinmodes()
374 		return data->rx_state;  in esai_get_state()
376 		return data->tx_state;  in esai_get_state()
390 		return -EPERM;  in esai_update_state()
395 			return -EPERM;  in esai_update_state()
401 			return -EPERM;  in esai_update_state()
406 			return -EPERM;  in esai_update_state()
411 		return -EINVAL;  in esai_update_state()
415 		data->rx_state = new_state;  in esai_update_state()
417 		data->tx_state = new_state;  in esai_update_state()
429 			base->RFCR |= ESAI_RFCR_RFE_MASK;  in esai_tx_rx_enable_disable_fifo()
431 			base->TFCR |= ESAI_TFCR_TFE_MASK;  in esai_tx_rx_enable_disable_fifo()
435 			base->RFCR &= ~ESAI_RFCR_RFE_MASK;  in esai_tx_rx_enable_disable_fifo()
437 			base->TFCR &= ~ESAI_TFCR_TFE_MASK;  in esai_tx_rx_enable_disable_fifo()
450 			base->RCR |= val;  in esai_tx_rx_enable_disable()
452 			base->TCR |= val;  in esai_tx_rx_enable_disable()
456 			base->RCR &= ~val;  in esai_tx_rx_enable_disable()
458 			base->TCR &= ~val;  in esai_tx_rx_enable_disable()
471 			base->RFCR |= val;  in esai_tx_rx_enable_disable_fifo_usage()
473 			base->TFCR |= val;  in esai_tx_rx_enable_disable_fifo_usage()
477 			base->RFCR &= ~val;  in esai_tx_rx_enable_disable_fifo_usage()
479 			base->TFCR &= ~val;  in esai_tx_rx_enable_disable_fifo_usage()
486 	LOG_DBG("HCLK prescaler enable: %d", cfg->hclk_prescaler_en);  in esai_dump_xceiver_config()
487 	LOG_DBG("HCLK divider ratio: %d", cfg->hclk_div_ratio);  in esai_dump_xceiver_config()
488 	LOG_DBG("BCLK divider ratio: %d", cfg->bclk_div_ratio);  in esai_dump_xceiver_config()
489 	LOG_DBG("HCLK bypass: %d", cfg->hclk_bypass);  in esai_dump_xceiver_config()
491 	LOG_DBG("HCLK direction: %d", cfg->hclk_dir);  in esai_dump_xceiver_config()
492 	LOG_DBG("HCLK source: %d", cfg->hclk_src);  in esai_dump_xceiver_config()
493 	LOG_DBG("HCLK polarity: %d", cfg->hclk_polarity);  in esai_dump_xceiver_config()
495 	LOG_DBG("BCLK direction: %d", cfg->bclk_dir);  in esai_dump_xceiver_config()
496 	LOG_DBG("BCLK polarity: %d", cfg->bclk_polarity);  in esai_dump_xceiver_config()
498 	LOG_DBG("FSYNC direction: %d", cfg->fsync_dir);  in esai_dump_xceiver_config()
499 	LOG_DBG("FSYNC polarity: %d", cfg->fsync_polarity);  in esai_dump_xceiver_config()
501 	LOG_DBG("FSYNC is bit wide: %d", cfg->fsync_is_bit_wide);  in esai_dump_xceiver_config()
502 	LOG_DBG("zero pad enable: %d", cfg->zero_pad_en);  in esai_dump_xceiver_config()
503 	LOG_DBG("FSYNC asserted early: %d", cfg->fsync_early);  in esai_dump_xceiver_config()
505 	LOG_DBG("watermark: %d", cfg->watermark);  in esai_dump_xceiver_config()
506 	LOG_DBG("slot mask: 0x%x", cfg->slot_mask);  in esai_dump_xceiver_config()
507 	LOG_DBG("word alignment: 0x%x", cfg->word_alignment);  in esai_dump_xceiver_config()
512 	LOG_DBG("ECR: 0x%x", base->ECR);  in esai_dump_register_data()
513 	LOG_DBG("ESR: 0x%x", base->ESR);  in esai_dump_register_data()
514 	LOG_DBG("TFCR: 0x%x", base->TFCR);  in esai_dump_register_data()
515 	LOG_DBG("TFSR: 0x%x", base->TFSR);  in esai_dump_register_data()
516 	LOG_DBG("RFCR: 0x%x", base->RFCR);  in esai_dump_register_data()
517 	LOG_DBG("RFSR: 0x%x", base->RFSR);  in esai_dump_register_data()
518 	LOG_DBG("TSR: 0x%x", base->TSR);  in esai_dump_register_data()
519 	LOG_DBG("SAISR: 0x%x", base->SAISR);  in esai_dump_register_data()
520 	LOG_DBG("SAICR: 0x%x", base->SAICR);  in esai_dump_register_data()
521 	LOG_DBG("TCR: 0x%x", base->TCR);  in esai_dump_register_data()
522 	LOG_DBG("TCCR: 0x%x", base->TCCR);  in esai_dump_register_data()
523 	LOG_DBG("RCR: 0x%x", base->RCR);  in esai_dump_register_data()
524 	LOG_DBG("RCCR: 0x%x", base->RCCR);  in esai_dump_register_data()
525 	LOG_DBG("TSMA: 0x%x", base->TSMA);  in esai_dump_register_data()
526 	LOG_DBG("TSMB: 0x%x", base->TSMB);  in esai_dump_register_data()
527 	LOG_DBG("RSMA: 0x%x", base->RSMA);  in esai_dump_register_data()
528 	LOG_DBG("RSMB: 0x%x", base->RSMB);  in esai_dump_register_data()
529 	LOG_DBG("PRRC: 0x%x", base->PRRC);  in esai_dump_register_data()
530 	LOG_DBG("PCRC: 0x%x", base->PCRC);  in esai_dump_register_data()