Lines Matching +full:fifo +full:- +full:depth
2 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
28 compatible = "arm,cortex-a9";
31 /* next-level-cache = <&L2>; */ /*cache driver not available yet */
34 compatible = "arm,cortex-a9";
37 /* next-level-cache = <&L2>; */ /*cache driver not available yet */
42 compatible = "arm,gic-v1", "arm,gic";
43 #interrupt-cells = <4>;
44 interrupt-controller;
50 #address-cells = <1>;
51 #size-cells = <1>;
52 compatible = "simple-bus";
54 interrupt-parent = <&intc>;
57 L2: l2-cache@fffef000 {
58 compatible = "arm,pl330-cache";
65 compatible = "altr,clk-mgr";
69 #clock-cells = <0>;
70 compatible = "fixed-clock";
73 #clock-cells = <0>;
74 compatible = "fixed-clock";
75 clock-frequency = <25000000>;
78 #clock-cells = <0>;
79 compatible = "fixed-clock";
80 clock-frequency = <50000000>;
83 #clock-cells = <0>;
84 compatible = "fixed-clock";
85 clock-frequency = <100000000>;
91 compatible = "altr,sys-mgr", "syscon";
96 compatible = "zephyr,memory-region" , "mmio-sram";
98 zephyr,memory-region = "OCRAM";
102 compatible = "arm,armv8-timer";
104 interrupt-names = "irq_0", "irq_1", "irq_2", "irq_3";
118 compatible = "ns16550","snps,dw-apb-uart";
121 reg-shift = <2>;
122 clock-frequency = <100000000>;
123 dma-names = "tx", "rx";
127 compatible = "ns16550","snps,dw-apb-uart";
130 reg-shift = <2>;
131 clock-frequency = <100000000>;
132 dma-names = "tx", "rx";
136 compatible = "snps,ethernet-cyclonev";
139 emac-index = <0>;
144 compatible = "snps,ethernet-cyclonev";
147 emac-index = <1>;
152 #address-cells = <1>;
153 #size-cells = <0>;
154 compatible = "snps,designware-gpio";
159 gpio-controller;
160 #gpio-cells = <2>;
164 #address-cells = <1>;
165 #size-cells = <0>;
166 compatible = "snps,designware-gpio";
171 gpio-controller;
172 #gpio-cells = <2>;
176 #address-cells = <1>;
177 #size-cells = <0>;
178 compatible = "snps,designware-gpio";
183 gpio-controller;
184 #gpio-cells = <2>;
188 #address-cells = <1>;
189 #size-cells = <0>;
190 compatible = "snps,designware-i2c";
192 clock-frequency = <I2C_BITRATE_STANDARD>;
194 interrupt-parent = <&intc>;
199 #address-cells = <1>;
200 #size-cells = <0>;
201 compatible = "snps,designware-i2c";
208 #address-cells = <1>;
209 #size-cells = <0>;
210 compatible = "snps,designware-i2c";
217 #address-cells = <1>;
218 #size-cells = <0>;
219 compatible = "snps,designware-i2c";
229 interrupt-parent = <&intc>;
230 num-out-eps = <16>;
231 num-in-eps = <16>;
242 interrupt-parent = <&intc>;
243 num-out-eps = <16>;
244 num-in-eps = <16>;
252 compatible = "snps,designware-spi";
253 #address-cells = <1>;
254 #size-cells = <0>;
256 fifo-depth = <256>;
257 max-xfer-size = <32>;
259 clock-frequency = <200000000>;
264 compatible = "snps,designware-spi";
265 #address-cells = <1>;
266 #size-cells = <0>;
268 fifo-depth = <256>;
269 max-xfer-size = <32>;
271 clock-frequency = <200000000>;