Searched full:dividers (Results 1 – 25 of 42) sorted by relevance
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71 /** Dividers and frequency for GCLK0 */80 /** Dividers and frequency for GCLK1 */93 /** Dividers and frequency for GCLK3 */
85 /** Dividers and frequency for GCLK0 */94 /** Dividers and frequency for GCLK1 */107 /** Dividers and frequency for GCLK3 */
91 /** Dividers and frequency for GCLK0 */100 /** Dividers and frequency for GCLK1 */113 /** Dividers and frequency for GCLK3 */
2 # for platforms that do not allow frequency dividers large enough to get
22 * Xilinx's emacps driver doesn't (or no longer does) limit the range of dividers24 * -> Contrary to earlier revisions of this driver, all dividers are available
21 uint8_t DIVIDERS[] = { 0x00, /* 2 */ variable82 sys_write8((DIVIDERS[i] >> 4) & 0x3, SPI_OC_SIMPLE_SPER(info)); in spi_oc_simple_configure()83 spcr |= (DIVIDERS[i] & 0x3); in spi_oc_simple_configure()
44 /* 0x010: HFCG Bus Clock Dividers */47 /* 0x012: HFCG Bus Clock Dividers */50 /* 0x014: HFCG Bus Clock Dividers */53 /* 0x01d: HFCG Bus Clock Dividers */
72 Some peripherals are sourced through fixed clock dividers. For such cases there is
139 } dividers[] = { in find_suitable_clock() local155 for (uint8_t d = 0; (best_diff != 0) && (d < ARRAY_SIZE(dividers)); ++d) { in find_suitable_clock()157 src_freq / dividers[d].divider_val; in find_suitable_clock()166 best_mck_cfg = dividers[d].divider_enum; in find_suitable_clock()172 /* Since dividers are in ascending order, stop in find_suitable_clock()
268 * dividers. SAF HW uses CS0/CS1 divider register fields to overwrite in saf_qmspi_init()270 * SAF CS0/CS1 SPI frequency dividers based on flash configuration. in saf_qmspi_init()273 qfdiv = qfdiv | (qfdiv << 16); /* read and rest clock dividers */ in saf_qmspi_init()445 /* Configure SAF per chip select QMSPI clock dividers.509 * SAF CS0 QMSPI frequency dividers (read/all other) commands510 * SAF CS1 QMSPI frequency dividers (read/all other) commands
86 * and once it's in use, it can be adjusted only with dividers.
70 /* Set up dividers */ in clock_init()
161 /* Reset clock dividers to 0 */ in soc_early_init_hook()
234 /* Set up dividers */ in clock_init()328 /* Using the Audio PLL as input clock leads to better clock dividers in clock_init()
88 /* Set the system clock dividers in SIM to safe value. */ in clock_init()
32 /* Other boards may use dividers that only reduce battery voltage to
65 /*!< Set up dividers */ in frdm_mcxa156_init()
162 /* Configure CPU clock dividers */ in init_cycfg_platform()
77 * WORKAROUND: stm32l4-pll-clock does not allow arbitrary PLLP dividers.
326 /* All dividers other than 0 use an addition of 2 + noise_filter_stages. */ in calc_iic_master_bitrate()389 /* All dividers other than 0 use an addition of 2 + noise_filter_stages. in calc_iic_master_clock_setting()
