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/Zephyr-latest/dts/bindings/pwm/
Draspberrypi,pico-pwm.yaml17 divider-int-0:
20 The integral part of the divider for pwm slice 0.
22 as the integer part of the divider.
26 divider-frac-0:
29 The fractional part of the divider for pwm slice 0.
31 When the "divider-int-0" is set to 0 or is not defined, this property will be
34 divider-int-1:
36 description: See divider-int-0 for help
38 divider-frac-1:
40 description: See divider-frac-0 for help
[all …]
Dinfineon,cat1-pwm.yaml39 divider-type:
42 Specifies which type of divider to use.
46 divider-sel:
49 Specifies which divider of the selected type to configure.
52 divider-val:
55 Causes integer division of (divider value + 1), or division by 1 to 256
56 (8-bit divider) or 1 to 65536 (16-bit divider).
/Zephyr-latest/tests/drivers/sensor/adltc2990/boards/
Dnative_sim.overlay13 pin-v1-voltage-divider-resistors = <500 1000>;
14 pin-v2-voltage-divider-resistors = <110000 100000>;
15 pin-v3-voltage-divider-resistors = <7000 1000>;
16 pin-v4-voltage-divider-resistors = <500 1000>;
27 pin-v1-voltage-divider-resistors = <0 1>;
28 pin-v2-voltage-divider-resistors = <0 1>;
29 pin-v3-voltage-divider-resistors = <0 1>;
30 pin-v4-voltage-divider-resistors = <0 1>;
39 pin-v1-voltage-divider-resistors = <0 1>;
40 pin-v2-voltage-divider-resistors = <0 1>;
[all …]
/Zephyr-latest/soc/nxp/rw/
Dflexspi_clock_setup.c18 * the FlexSPI with a new MUX source, only change the divider. This function
25 uint32_t divider; in flexspi_clock_set_freq() local
33 /* Select a divider based on root frequency. in flexspi_clock_set_freq()
34 * if we can't get an exact divider, round down in flexspi_clock_set_freq()
36 divider = ((root_rate + (rate - 1)) / rate) - 1; in flexspi_clock_set_freq()
37 /* Cap divider to max value */ in flexspi_clock_set_freq()
38 divider = MIN(divider, CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK); in flexspi_clock_set_freq()
46 CLKCTL0_FLEXSPIFCLKSEL_SEL_MASK), (divider + 1)); in flexspi_clock_set_freq()
60 void __ramfunc set_flexspi_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider) in set_flexspi_clock() argument
64 CLKCTL0_FLEXSPIFCLKDIV_RESET_MASK; /* Reset the divider counter */ in set_flexspi_clock()
[all …]
/Zephyr-latest/soc/nxp/mcx/mcxn/
Dflash_clock_setup.c12 uint8_t divider; in flexspi_clock_set_freq() local
17 divider = ((pll_rate + (rate - 1)) / rate) - 1; in flexspi_clock_set_freq()
18 /* Max divider value is 8 */ in flexspi_clock_set_freq()
19 divider = MIN(divider, 8); in flexspi_clock_set_freq()
20 SYSCON->FLEXSPICLKDIV = divider; in flexspi_clock_set_freq()
/Zephyr-latest/dts/bindings/iio/afe/
Dvoltage-divider.yaml5 Description for a voltage divider, with optional ability to measure
8 compatible: "voltage-divider"
16 Channels available with this divider configuration.
22 Resistance of the lower leg of the voltage divider
27 Resistance of the full path through the voltage divider.
35 Control power to the voltage divider inputs.
38 to enable the divider input.
/Zephyr-latest/soc/nxp/imxrt/imxrt10xx/
Dflexspi.c16 uint8_t divider; in flexspi_clock_set_freq() local
44 /* Select a divider based on root frequency. in flexspi_clock_set_freq()
45 * if we can't get an exact divider, round down in flexspi_clock_set_freq()
47 divider = ((root_rate + (rate - 1)) / rate) - 1; in flexspi_clock_set_freq()
48 /* Cap divider to max value */ in flexspi_clock_set_freq()
49 divider = MIN(divider, kCLOCK_FlexspiDivBy8); in flexspi_clock_set_freq()
58 CLOCK_SetDiv(div_sel, divider); in flexspi_clock_set_freq()
/Zephyr-latest/soc/nxp/imxrt/imxrt118x/
Dflexspi.c21 uint32_t divider; in flexspi_clock_set_freq() local
41 /* Select a divider based on root clock frequency. We round the in flexspi_clock_set_freq()
42 * divider up, so that the resulting clock frequency is lower than in flexspi_clock_set_freq()
45 divider = ((root_rate + (rate - 1)) / rate); in flexspi_clock_set_freq()
46 /* Cap divider to max value */ in flexspi_clock_set_freq()
47 divider = MIN(divider, CCM_CLOCK_ROOT_CONTROL_DIV_MASK); in flexspi_clock_set_freq()
56 CLOCK_SetRootClockDiv(flexspi_clk, divider); in flexspi_clock_set_freq()
/Zephyr-latest/soc/nxp/imxrt/imxrt11xx/
Dflexspi.c21 uint32_t divider; in flexspi_clock_set_freq() local
41 /* Select a divider based on root clock frequency. We round the in flexspi_clock_set_freq()
42 * divider up, so that the resulting clock frequency is lower than in flexspi_clock_set_freq()
45 divider = ((root_rate + (rate - 1)) / rate); in flexspi_clock_set_freq()
46 /* Cap divider to max value */ in flexspi_clock_set_freq()
47 divider = MIN(divider, CCM_CLOCK_ROOT_CONTROL_DIV_MASK); in flexspi_clock_set_freq()
56 CLOCK_SetRootClockDiv(flexspi_clk, divider); in flexspi_clock_set_freq()
/Zephyr-latest/dts/bindings/i3c/
Dnxp,mcux-i3c.yaml25 clk-divider:
27 description: Main clock divider for I3C
30 clk-divider-tc:
32 description: TC clock divider for I3C
35 clk-divider-slow:
37 description: Slow clock divider for I3C
/Zephyr-latest/drivers/mdio/
Dmdio_xmc4xxx.c30 uint8_t divider; member
35 {.divider = 8, .reg_val = 2}, {.divider = 13, .reg_val = 3},
36 {.divider = 21, .reg_val = 0}, {.divider = 31, .reg_val = 1},
37 {.divider = 51, .reg_val = 4}, {.divider = 62, .reg_val = 5},
125 uint8_t divider = mdio_clock_divider[i].divider; in mdio_xmc4xxx_set_clock_divider() local
127 uint32_t mdc_clk = eth_mac_clk / divider; in mdio_xmc4xxx_set_clock_divider()
130 LOG_DBG("Using MDC clock divider %d", divider); in mdio_xmc4xxx_set_clock_divider()
157 LOG_ERR("Error setting MDIO clock divider"); in mdio_xmc4xxx_initialize()
/Zephyr-latest/drivers/pwm/
Dpwm_sam.c30 uint8_t divider; member
38 uint8_t divider = config->divider; in sam_pwm_get_cycles_per_sec() local
41 ((1 << prescaler) * divider); in sam_pwm_get_cycles_per_sec()
101 uint8_t divider = config->divider; in sam_pwm_init() local
104 /* FIXME: way to validate prescaler & divider */ in sam_pwm_init()
116 pwm->PWM_CLK = PWM_CLK_PREA(prescaler) | PWM_CLK_DIVA(divider); in sam_pwm_init()
133 .divider = DT_INST_PROP(inst, divider), \
/Zephyr-latest/drivers/clock_control/
Dclock_control_si32_apb.c20 uint32_t divider; member
44 *rate /= config->divider; in clock_control_si32_apb_get_rate()
63 if (config->divider == 1) { in clock_control_si32_apb_init()
65 } else if (config->divider == 2) { in clock_control_si32_apb_init()
76 .divider = DT_PROP(DT_NODELABEL(clk_apb), divider),
Dclock_control_r8a779f0_cpg_mssr.c178 /* real divider is in range 4 - 6 */ in r8a779f0_get_div_helper()
182 LOG_WRN("SDSRC clock has an incorrect divider value: %u", reg_val); in r8a779f0_get_div_helper()
192 LOG_WRN("SD0H clock has an incorrect divider value: %u", reg_val); in r8a779f0_get_div_helper()
202 static int r8a779f0_set_rate_helper(uint32_t module, uint32_t *divider, uint32_t *div_mask) in r8a779f0_set_rate_helper() argument
206 /* divider has to be in range 4-6 */ in r8a779f0_set_rate_helper()
207 if (*divider > 3 && *divider < 7) { in r8a779f0_set_rate_helper()
209 *divider -= 4; in r8a779f0_set_rate_helper()
210 *divider <<= R8A779F0_CLK_SDSRC_DIV_SHIFT; in r8a779f0_set_rate_helper()
217 if (*divider == 2 || *divider == 4) { in r8a779f0_set_rate_helper()
219 *divider >>= 2; in r8a779f0_set_rate_helper()
[all …]
Dclock_control_lpc11u6x.h79 volatile uint32_t sys_ahb_clk_div; /* System clock divider */
83 volatile uint32_t ssp0_clk_div; /* SSP0 clock divider */
84 volatile uint32_t usart0_clk_div; /* USART0 clock divider */
85 volatile uint32_t ssp1_clk_div; /* SSP1 clock divider */
87 * rate generator clock divider
92 volatile uint32_t usb_clk_div; /* USB clock divider */
96 volatile uint32_t clk_out_div; /* CLKOUT divider */
99 * generator divider
110 volatile uint32_t iocon_clk_div[7]; /* IOCON clock divider */
Dclock_control_r8a7795_cpg_mssr.c194 /* according to documentation, divider value stored in reg is equal to: val + 1 */ in r8a7795_get_div_helper()
204 static int r8a7795_set_rate_helper(uint32_t module, uint32_t *divider, uint32_t *div_mask) in r8a7795_set_rate_helper() argument
212 if (*divider == 2 || *divider == 4) { in r8a7795_set_rate_helper()
214 *divider >>= 2; in r8a7795_set_rate_helper()
224 /* divider should be power of two and max possible value 16 */ in r8a7795_set_rate_helper()
225 if (!is_power_of_two(*divider) || *divider > 16) { in r8a7795_set_rate_helper()
230 *divider = (find_lsb_set(*divider) - 1) << R8A7795_CLK_SDH_DIV_SHIFT; in r8a7795_set_rate_helper()
234 /* according to documentation, divider value stored in reg is equal to: val + 1 */ in r8a7795_set_rate_helper()
235 *divider -= 1; in r8a7795_set_rate_helper()
236 if (*divider <= R8A7795_CLK_CANFD_DIV_MASK) { in r8a7795_set_rate_helper()
Dclock_control_renesas_cpg_mssr.c94 uint32_t divider = RCAR_CPG_NONE; in rcar_cpg_get_divider() local
111 divider = data->get_div_helper(reg_val, clk_info->module); in rcar_cpg_get_divider()
114 if (!divider) { in rcar_cpg_get_divider()
118 return divider; in rcar_cpg_get_divider()
123 uint32_t divider = rcar_cpg_get_divider(dev, clk_info); in rcar_cpg_update_out_freq() local
125 if (divider == RCAR_CPG_NONE) { in rcar_cpg_update_out_freq()
129 clk_info->out_freq = clk_info->in_freq / divider; in rcar_cpg_update_out_freq()
196 * - divider is zero (with current implementation of board specific in rcar_cpg_change_children_in_out_freq()
197 * divider helper function it is impossible); in rcar_cpg_change_children_in_out_freq()
198 * - we don't have board specific implementation of get divider helper in rcar_cpg_change_children_in_out_freq()
[all …]
/Zephyr-latest/dts/bindings/clock/
Dlitex,clk.yaml47 minimal global divider
52 maximal global divider
67 minimal frequency after global divider and multiplier
72 maximal frequency after global divider and multiplier
77 minimal clock output divider
82 maximal clock output divider
Draspberrypi,pico-pll.yaml16 The feedback divider value.
23 The post clock divider.
30 The post clock divider.
/Zephyr-latest/soc/nxp/kinetis/k8x/
DKconfig35 int "Freescale K8x core clock divider"
42 int "Freescale K8x bus clock divider"
49 int "Freescale K8x FlexBus clock divider"
56 int "Freescale K8x flash clock divider"
/Zephyr-latest/samples/boards/nordic/battery/
DREADME.rst14 ``voltage-divider`` then the voltage is measured using that divider. An
15 example of a devicetree node describing a voltage divider for battery
22 compatible = "voltage-divider";
30 * If the board does not have a voltage divider and so no ``/vbatt`` node
45 Note that in many cases where there is no voltage divider the digital
66 A Nordic-based board, optionally with a voltage divider specified in its
/Zephyr-latest/samples/sensor/lps22hh_i3c/boards/
Dmimxrt685_evk_mimxrt685s_cm33.overlay14 clk-divider = <12>;
15 clk-divider-slow = <1>;
16 clk-divider-tc = <1>;
/Zephyr-latest/samples/sensor/lsm6dso_i2c_on_i3c/boards/
Dmimxrt685_evk_mimxrt685s_cm33.overlay14 clk-divider = <12>;
15 clk-divider-slow = <1>;
16 clk-divider-tc = <1>;
/Zephyr-latest/dts/bindings/timer/
Dambiq,stimer.yaml24 1 - HFRC_DIV16 : 3MHz from the HFRC clock divider.
25 2 - HFRC_DIV256 : 187.5KHz from the HFRC clock divider.
34 1 - HFRC_6MHZ : 6MHz from the HFRC clock divider.
35 2 - HFRC_375KHZ : 375KHz from the HFRC clock divider.
/Zephyr-latest/samples/basic/fade_led/boards/
Dcyw920829m2evk_02.overlay29 divider-type = <CY_SYSCLK_DIV_16_BIT>;
30 divider-sel = <1>;
31 divider-val = <9599>;

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