94 	uint32_t divider = RCAR_CPG_NONE;  in rcar_cpg_get_divider()  local
111 		divider = data->get_div_helper(reg_val, clk_info->module);  in rcar_cpg_get_divider()
114 	if (!divider) {  in rcar_cpg_get_divider()
118 	return divider;  in rcar_cpg_get_divider()
123 	uint32_t divider = rcar_cpg_get_divider(dev, clk_info);  in rcar_cpg_update_out_freq()  local
125 	if (divider == RCAR_CPG_NONE) {  in rcar_cpg_update_out_freq()
129 	clk_info->out_freq = clk_info->in_freq / divider;  in rcar_cpg_update_out_freq()
196 			 * - divider is zero (with current implementation of board specific  in rcar_cpg_change_children_in_out_freq()
197 			 *   divider helper function it is impossible);  in rcar_cpg_change_children_in_out_freq()
198 			 * - we don't have board specific implementation of get divider helper  in rcar_cpg_change_children_in_out_freq()
202 			 * - impossible value is set in clock register divider bits.  in rcar_cpg_change_children_in_out_freq()
204 			LOG_ERR("%s: error during getting divider from clock register, domain %u "  in rcar_cpg_change_children_in_out_freq()
205 				"module %u! Please, revise logic related to obtaining divider or "  in rcar_cpg_change_children_in_out_freq()
267 	uint32_t divider;  in rcar_cpg_set_rate()  local
302 	divider = in_freq / u_rate;  in rcar_cpg_set_rate()
303 	if (divider * u_rate != in_freq) {  in rcar_cpg_set_rate()
313 	ret = data->set_rate_helper(module, &divider, &div_mask);  in rcar_cpg_set_rate()
319 		rcar_cpg_write(DEVICE_MMIO_GET(dev), clk_info->offset, reg | divider);  in rcar_cpg_set_rate()