Lines Matching full:divider
178 /* real divider is in range 4 - 6 */ in r8a779f0_get_div_helper()
182 LOG_WRN("SDSRC clock has an incorrect divider value: %u", reg_val); in r8a779f0_get_div_helper()
192 LOG_WRN("SD0H clock has an incorrect divider value: %u", reg_val); in r8a779f0_get_div_helper()
202 static int r8a779f0_set_rate_helper(uint32_t module, uint32_t *divider, uint32_t *div_mask) in r8a779f0_set_rate_helper() argument
206 /* divider has to be in range 4-6 */ in r8a779f0_set_rate_helper()
207 if (*divider > 3 && *divider < 7) { in r8a779f0_set_rate_helper()
209 *divider -= 4; in r8a779f0_set_rate_helper()
210 *divider <<= R8A779F0_CLK_SDSRC_DIV_SHIFT; in r8a779f0_set_rate_helper()
217 if (*divider == 2 || *divider == 4) { in r8a779f0_set_rate_helper()
219 *divider >>= 2; in r8a779f0_set_rate_helper()
225 /* divider should be power of two number and last possible value 16 */ in r8a779f0_set_rate_helper()
226 if (!is_power_of_two(*divider) || *divider > 16) { in r8a779f0_set_rate_helper()
230 *divider = (find_lsb_set(*divider) - 1) << R8A779F0_CLK_SD0H_DIV_SHIFT; in r8a779f0_set_rate_helper()