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/Zephyr-latest/dts/bindings/tcpc/
Dnuvoton,numaker-tcpc.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Nuvoton NuMaker USB Type-C port controller
6 compatible: "nuvoton,numaker-tcpc"
8 include: [base.yaml, reset-device.yaml, pinctrl-device.yaml]
23 vconn-overcurrent-event-polarity:
28 - "low-active"
29 - "high-active"
31 vconn-discharge-polarity:
36 - "low-active"
37 - "high-active"
[all …]
/Zephyr-latest/scripts/kconfig/
Dkconfigfunctions.py1 # Copyright (c) 2018-2019 Linaro
4 # SPDX-License-Identifier: Apache-2.0
17 "python-devicetree", "src"))
47 return 20
157 foo: some-node { ... };
206 The function will divide the value based on 'unit':
208 'k' or 'K' divide by 1024 (1 << 10)
209 'm' or 'M' divide by 1,048,576 (1 << 20)
210 'g' or 'G' divide by 1,073,741,824 (1 << 30)
211 'kb' or 'Kb' divide by 8192 (1 << 13)
[all …]
/Zephyr-latest/dts/bindings/can/
Dst,stm32h7-fdcan.yaml3 compatible: "st,stm32h7-fdcan"
5 include: ["bosch,m_can-base.yaml", "pinctrl-device.yaml"]
17 interrupt-names:
20 clk-divider:
23 - 1
24 - 2
25 - 4
26 - 6
27 - 8
28 - 10
[all …]
Dst,stm32-fdcan.yaml3 compatible: "st,stm32-fdcan"
5 include: ["bosch,m_can-base.yaml", "pinctrl-device.yaml"]
14 interrupt-names:
20 clk-divider:
23 - 1
24 - 2
25 - 4
26 - 6
27 - 8
28 - 10
[all …]
Dmicrochip,mcp251xfd.yaml2 # SPDX-License-Identifier: Apache-2.0
11 cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>;
17 spi-max-frequency = <18000000>;
18 int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>;
20 osc-freq = <40000000>;
27 include: [spi-device.yaml, can-fd-controller.yaml]
30 osc-freq:
35 int-gpios:
36 type: phandle-array
39 The interrupt signal from the controller is active low in push-pull mode.
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dti,fdc2x1x.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [sensor-device.yaml, i2c-device.yaml]
11 sd-gpios:
12 type: phandle-array
18 intb-gpios:
19 type: phandle-array
28 Set to identify the sensor as FDC2114 or FDC2214 (4-channel version)
33 Set the Auto-Scan Mode.
36 "active-channel" (single channel mode).
38 true = Auto-Scan conversions as selected by "rr-sequence"
[all …]
/Zephyr-latest/dts/bindings/display/
Dled-strip-matrix.yaml2 # SPDX-License-Identifier: Apache-2.0
7 compatible: "led-strip-matrix"
9 include: display-controller.yaml
32 start-from-right:
49 start-from-bottom:
76 horizontal-modules:
82 The number must be able to divide the width value.
87 [ 7][ 6][ 5][ 4] [23][22][21][20]
91 vertical-modules:
97 The number must be able to divide the height value.
[all …]
/Zephyr-latest/arch/xtensa/core/
Dfatal.c3 * SPDX-License-Identifier: Apache-2.0
36 return "level-1 interrupt"; in xtensa_exccause()
40 return "divide by zero"; in xtensa_exccause()
59 case 20: in xtensa_exccause()
128 xtensa_simulator_exit(255 - reason); in arch_system_halt()
143 if ((arch_current_thread()->base.user_options & K_USER) != 0) { in z_impl_xtensa_user_fault()
/Zephyr-latest/soc/nxp/imxrt/imxrt10xx/
Dsoc.c2 * Copyright 2017-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/linker/linker-defs.h>
18 #include <zephyr/dt-bindings/clock/imx_ccm.h>
46 .loopDivider = (DT_PROP(DT_CHILD(CCM_NODE, sys_pll), loop_div) - 20) / 2,
156 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(CONFIG_DCDC_VALUE); in clock_init()
159 (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) { in clock_init()
180 CLOCK_SetDiv(kCLOCK_ArmDiv, DT_PROP(DT_CHILD(CCM_NODE, arm_podf), clock_div) - 1); in clock_init()
184 CLOCK_SetDiv(kCLOCK_AhbDiv, DT_PROP(DT_CHILD(CCM_NODE, ahb_podf), clock_div) - 1); in clock_init()
187 CLOCK_SetDiv(kCLOCK_IpgDiv, DT_PROP(DT_CHILD(CCM_NODE, ipg_podf), clock_div) - 1); in clock_init()
[all …]
/Zephyr-latest/subsys/bluetooth/common/
DKconfig5 # SPDX-License-Identifier: Apache-2.0
21 In a Host-only build the Host will read the maximum ACL size supported
47 determines how to divide the buffers between the connections.
109 enforced by a build-time check: BT_BUF_ACL_RX_COUNT needs to be at
130 default 20 if (BT_MESH && !(BT_BUF_EVT_DISCARDABLE_COUNT > 0))
156 default 20 if BT_MESH
195 ZEPHYR_BT_HCI := zephyr,bt-hci
199 default $(dt_chosen_bool_prop,$(ZEPHYR_BT_HCI),bt-hci-vs-ext)
202 for the Zephyr HCI Vendor-Specific Commands and Event.
205 bool "Zephyr HCI Vendor-Specific Commands"
[all …]
/Zephyr-latest/drivers/i2c/
Di2c_esp32.c5 * SPDX-License-Identifier: Apache-2.0
10 /* Include esp-idf headers first to avoid redefining BIT() macro */
31 #include "i2c-priv.h"
39 #define I2C_CLK_LIMIT_REF_TICK (1 * 1000 * 1000 / 20) /* REF_TICK, no more than REF_TICK/20*/
40 #define I2C_CLK_LIMIT_APB (80 * 1000 * 1000 / 20) /* Limited by APB, no more than APB/20 */
41 #define I2C_CLK_LIMIT_RTC (20 * 1000 * 1000 / 20) /* Limited by RTC, no more than RTC/20 */
42 #define I2C_CLK_LIMIT_XTAL (40 * 1000 * 1000 / 20) /* Limited by RTC, no more than XTAL/20 */
44 #define I2C_CLOCK_INVALID (-1)
139 /* I2C SCL clock frequency should not larger than clock source frequency/20 */ in i2c_get_clk_src()
140 if (clk_freq <= (i2c_get_src_clk_freq(clk_srcs[i]) / 20)) { in i2c_get_clk_src()
[all …]
/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dsoc.c2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
11 * This module provides routines to initialize and support board-level
55 /* Divide by 22 */
65 /* Divide by 22 */
176 /* Wait until host_needclk de-asserts */ in usb_device_clock_init()
177 while (SYSCTL0->USB0CLKSTAT & SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK) { in usb_device_clock_init()
183 USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; in usb_device_clock_init()
203 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; in soc_reset_hook()
270 /* Set up clock selectors - Attach clocks to the peripheries. */ in rt5xx_clock_init()
[all …]
/Zephyr-latest/soc/nxp/rw/
Dsoc.c2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
79 * clock needs to be re-initialized on exit from Standby mode. Hence
86 if ((PMU->CAU_SLP_CTRL & PMU_CAU_SLP_CTRL_SOC_SLP_RDY_MASK) == 0U) { in clock_init()
90 if ((SYSCTL2->SOURCE_CLK_GATE & SYSCTL2_SOURCE_CLK_GATE_REFCLK_SYS_CG_MASK) != 0U) { in clock_init()
136 /* Set PLL FRG clock to 20MHz. */ in clock_init()
227 * channel 1, which is clocked at 12.288 MHz. We can divide this in clock_init()
256 SYSCTL2->ANA_GRP_CTRL |= SYSCTL2_ANA_GRP_CTRL_PU_AG_MASK; in clock_init()
/Zephyr-latest/dts/arm/nxp/
Dnxp_rt1010.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 flexram,num-ram-banks = <4>;
12 flexram,bank-spec = <FLEXRAM_OCRAM>,
19 clock-frequency = <500000000>;
35 /delete-node/ arm-podf;
37 ipg-podf {
38 clock-div = <4>;
61 irq-shared-offset = <0>;
62 dma-channels = <16>;
67 /* Remove GPIO3-GPIO9, they don't exist on RT1010 */
[all …]
Dnxp_rt10xx.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/imx_ccm.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/memory-controller/nxp,flexram.h>
19 die-temp0 = &tempmon;
23 #address-cells = <1>;
[all …]
/Zephyr-latest/scripts/pylib/twister/twisterlib/
Dsize_calc.py5 # SPDX-License-Identifier: Apache-2.0
73 # These get copied into RAM only on non-XIP
168 def get_available_ram(self) -> int:
175 def get_available_rom(self) -> int:
192 def _check_elf_file(self) -> None:
204 def _check_is_xip(self) -> None:
212 "utf-8").strip()
222 def _get_info_elf_sections(self) -> None:
224 objdump_command = "objdump -h " + self.elf_filename
226 objdump_command, shell=True).decode("utf-8").splitlines()
[all …]
/Zephyr-latest/include/zephyr/usb/class/
Dhid.h5 * SPDX-License-Identifier: Apache-2.0
13 * Version 1.11 document (HID1_11-1.pdf).
231 * @brief Define HID End Collection (non-data) item.
447 HID_REPORT_SIZE(8 - bcnt), \
456 HID_LOGICAL_MIN8(-127), \
535 HID_KEY_Q = 20,
565 HID_KEY_HASH = 50, /* Non-US # and ~ */
599 HID_KEY_KPSLASH = 84, /* NUMPAD DIVIDE */
/Zephyr-latest/drivers/dai/nxp/esai/
Desai.c4 * SPDX-License-Identifier: Apache-2.0
25 * by 1 up to 256 (configured via xPM0-xPM7). The resulting
28 * up to 16 (configured via xFP0-xFP3). The resulting signal is
42 return -EINVAL; in esai_get_clock_rate_config()
47 return -EINVAL; in esai_get_clock_rate_config()
52 return -EINVAL; in esai_get_clock_rate_config()
57 return -EINVAL; in esai_get_clock_rate_config()
63 return -EINVAL; in esai_get_clock_rate_config()
69 return -EINVAL; in esai_get_clock_rate_config()
80 return -EINVAL; in esai_get_clock_rate_config()
[all …]
/Zephyr-latest/drivers/flash/
Dflash_cadence_qspi_nor_ll.c4 * SPDX-License-Identifier: Apache-2.0
20 return -EINVAL; in cad_qspi_idle()
23 return (sys_read32(cad_params->reg_base + CAD_QSPI_CFG) & CAD_QSPI_CFG_IDLE) >> 31; in cad_qspi_idle()
30 return -EINVAL; in cad_qspi_set_baudrate_div()
37 sys_clear_bits(cad_params->reg_base + CAD_QSPI_CFG, ~CAD_QSPI_CFG_BAUDDIV_MSK); in cad_qspi_set_baudrate_div()
39 sys_set_bits(cad_params->reg_base + CAD_QSPI_CFG, CAD_QSPI_CFG_BAUDDIV(div)); in cad_qspi_set_baudrate_div()
49 return -EINVAL; in cad_qspi_configure_dev_size()
55 cad_params->reg_base + CAD_QSPI_DEVSZ); in cad_qspi_configure_dev_size()
65 return -EINVAL; in cad_qspi_set_read_config()
72 cad_params->reg_base + CAD_QSPI_DEVRD); in cad_qspi_set_read_config()
[all …]
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/
Dull_conn.c2 * Copyright (c) 2018-2021 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
195 if (conn->lll.handle != handle) { in ll_connected_get()
230 return -EINVAL; in ll_tx_mem_enqueue()
235 return -ENOBUFS; in ll_tx_mem_enqueue()
238 lll_tx->handle = handle; in ll_tx_mem_enqueue()
239 lll_tx->node = tx; in ll_tx_mem_enqueue()
244 if (ull_ref_get(&conn->ull)) { in ll_tx_mem_enqueue()
249 force_md_cnt = force_md_cnt_calc(&conn->lll, tx_rate); in ll_tx_mem_enqueue()
266 if (IS_ENABLED(CONFIG_BT_PERIPHERAL) && conn->lll.role) { in ll_tx_mem_enqueue()
[all …]
/Zephyr-latest/drivers/sdhc/
Dsdhc_esp32.c4 * SPDX-License-Identifier: Apache-2.0
81 uint32_t bus_clock; /* Value in Hz. ESP-IDF functions use kHz instead */
98 * - one is the clock generator which drives SDMMC peripheral,
99 * it can be configured using sdio_hw->clock register. It can generate
101 * - 4 clock dividers inside SDMMC peripheral, which can divide clock
105 * For cards which aren't UHS-1 or UHS-2 cards, which we don't support,
107 * Note: for non-UHS-1 cards, HS mode is optional.
140 sdio_hw->ctrl.dma_enable = 1; in sdmmc_host_dma_init()
141 sdio_hw->bmod.val = 0; in sdmmc_host_dma_init()
142 sdio_hw->bmod.sw_reset = 1; in sdmmc_host_dma_init()
[all …]
/Zephyr-latest/subsys/bluetooth/mesh/
Dproxy_srv.c5 * SPDX-License-Identifier: Apache-2.0
72 [0 ... (CONFIG_BT_MAX_CONN - 1)] = {
92 return -EINVAL; in gatt_recv()
97 return -EINVAL; in gatt_recv()
111 if (buf->len < 1) { in filter_set()
113 return -EINVAL; in filter_set()
121 (void)memset(client->filter, 0, sizeof(client->filter)); in filter_set()
122 client->filter_type = ACCEPT; in filter_set()
125 (void)memset(client->filter, 0, sizeof(client->filter)); in filter_set()
126 client->filter_type = REJECT; in filter_set()
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_control_litex.c4 * SPDX-License-Identifier: Apache-2.0
66 …* https://github.com/Digilent/Zybo-hdmi-out/blob/b991fff6e964420ae3c00c3dbee52f2ad748b3ba/sdk/disp…
213 return litex_clk_filter_table[glob_mul - 1]; in litex_clk_lookup_filter()
219 return litex_clk_lock_table[glob_mul - 1]; in litex_clk_lookup_lock()
234 int assert = (1 << (drp[reg].size * BITS_PER_BYTE)) - 1; in litex_clk_assert_reg()
251 timeout = ldev->timeout.lock; in litex_clk_wait()
253 timeout = ldev->timeout.drdy; in litex_clk_wait()
257 timeout--; in litex_clk_wait()
262 return -ETIME; in litex_clk_wait()
303 ldev->g_config.mul = 1; in litex_clk_update_global_config()
[all …]
/Zephyr-latest/drivers/adc/
Dadc_stm32.c9 * SPDX-License-Identifier: Apache-2.0
46 #include <zephyr/dt-bindings/adc/stm32_adc.h>
51 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
56 #include <zephyr/linker/linker-defs.h>
81 * compat st_stm32f1_adc -> STM32F1, F37x (ADC1_V2_5)
82 * compat st_stm32f4_adc -> STM32F2, F4, F7, L1
196 /* Allow ADC to create DMA request and set to one-shot mode as implemented in HAL drivers */ in adc_stm32_enable_dma_support()
213 const struct adc_stm32_cfg *config = dev->config; in adc_stm32_dma_start()
214 ADC_TypeDef *adc = config->base; in adc_stm32_dma_start()
215 struct adc_stm32_data *data = dev->data; in adc_stm32_dma_start()
[all …]
/Zephyr-latest/drivers/usb_c/tcpc/
Ducpd_numaker.c4 * SPDX-License-Identifier: Apache-2.0
36 * by Timer-trigger EADC. To implement this interconnection, TCPC node_id
39 * NOTE: EADC and Timer interrupts needn't enable for Timer-triggered EADC.
49 * (1) DPM-supplied callback
76 #define NUMAKER_SYS_REG_DUMP(dev, reg_name) LOG_INF("SYS: %8s: 0x%08x", #reg_name, SYS->reg_name);
82 LOG_INF("%s: %8s: 0x%08x", #port, #reg_name, port->reg_name);
98 utcpd_base->reg_name = (val); \
110 LOG_ERR("UTCPD register (%s) write timeout, force-write", #reg_name); \
112 utcpd_base->reg_name = (val); \
137 LOG_ERR("UTCPD register (0x%04x) write timeout, force-write", reg_offset); \
[all …]

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