Lines Matching +full:divide +full:- +full:20
2 * Copyright 2017-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/linker/linker-defs.h>
18 #include <zephyr/dt-bindings/clock/imx_ccm.h>
46 .loopDivider = (DT_PROP(DT_CHILD(CCM_NODE, sys_pll), loop_div) - 20) / 2,
156 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(CONFIG_DCDC_VALUE); in clock_init()
159 (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) { in clock_init()
180 CLOCK_SetDiv(kCLOCK_ArmDiv, DT_PROP(DT_CHILD(CCM_NODE, arm_podf), clock_div) - 1); in clock_init()
184 CLOCK_SetDiv(kCLOCK_AhbDiv, DT_PROP(DT_CHILD(CCM_NODE, ahb_podf), clock_div) - 1); in clock_init()
187 CLOCK_SetDiv(kCLOCK_IpgDiv, DT_PROP(DT_CHILD(CCM_NODE, ipg_podf), clock_div) - 1); in clock_init()
219 /* Divide output by 2 */ in clock_init()
221 /* Set final div based on LCDIF clock-frequency */ in clock_init()
225 clock_frequency)) - 1); in clock_init()
296 /* Divide root clock output by 3 */ in clock_init()