Lines Matching +full:divide +full:- +full:20

2 # SPDX-License-Identifier: Apache-2.0
11       cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>;
17           spi-max-frequency = <18000000>;
18           int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>;
20           osc-freq = <40000000>;
27 include: [spi-device.yaml, can-fd-controller.yaml]
30   osc-freq:
35   int-gpios:
36     type: phandle-array
39       The interrupt signal from the controller is active low in push-pull mode.
43   pll-enable:
52   timestamp-prescaler:
60   sof-on-clko:
63       Output start-of-frame (SOF) signal on the CLKO pin every time
65       is not set, then an internal clock (typically 40MHz or 20MHz) will be
68   clko-div:
70     description: The factor to divide the system clock for CLKO pin.
73       - 1
74       - 2
75       - 4
76       - 10