| /Zephyr-latest/include/zephyr/sys/ |
| D | sys_io.h | 6 * SPDX-License-Identifier: Apache-2.0
26 * @fn static inline void sys_out8(uint8_t data, io_port_t port);
31 * @param data the byte to write
47 * @fn static inline void sys_out16(uint16_t data, io_port_t port);
48 * @brief Output a 16 bits to an I/O port
50 * This function writes a 16 bits to the given port.
52 * @param data the 16 bits to write
53 * @param port the port address where to write the 16 bits
58 * @brief Input 16 bits from an I/O port
60 * This function reads 16 bits from the port.
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| /Zephyr-latest/include/zephyr/drivers/mfd/ |
| D | npm1300.h | 3 * SPDX-License-Identifier: Apache-2.0
47 * @param base Register base address (bits 15..8 of 16-bit address)
48 * @param offset Register offset address (bits 7..0 of 16-bit address)
49 * @param data Pointer to buffer for received data
52 * @retval -errno In case of any bus error (see i2c_write_read_dt())
54 int mfd_npm1300_reg_read_burst(const struct device *dev, uint8_t base, uint8_t offset, void *data,
61 * @param base Register base address (bits 15..8 of 16-bit address)
62 * @param offset Register offset address (bits 7..0 of 16-bit address)
63 * @param data Pointer to buffer for received data
65 * @retval -errno In case of any bus error (see i2c_write_read_dt())
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| /Zephyr-latest/include/zephyr/drivers/misc/ft8xx/ |
| D | ft8xx_common.h | 4 * SPDX-License-Identifier: Apache-2.0
29 * @brief Write 1 byte (8 bits) to FT8xx memory
32 * @param data Byte to write
34 void ft8xx_wr8(uint32_t address, uint8_t data);
37 * @brief Write 2 bytes (16 bits) to FT8xx memory
40 * @param data Value to write
42 void ft8xx_wr16(uint32_t address, uint16_t data);
45 * @brief Write 4 bytes (32 bits) to FT8xx memory
48 * @param data Value to write
50 void ft8xx_wr32(uint32_t address, uint32_t data);
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| /Zephyr-latest/include/zephyr/drivers/ |
| D | swdp.h | 4 * SPDX-License-Identifier: Apache-2.0
21 /* SWDP packet request bits */
27 /* SWDP acknowledge response bits */
46 * @brief Write count bits to SWDIO from data LSB first
49 * @param count Number of bits to write
50 * @param data Bits to write
55 const uint8_t *data);
58 * @brief Read count bits from SWDIO into data LSB first
61 * @param count Number of bits to read
62 * @param data Buffer to store bits read
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| /Zephyr-latest/subsys/bluetooth/controller/util/ |
| D | util.c | 5 * SPDX-License-Identifier: Apache-2.0
24 * @brief Population count: Count the number of bits set to 1
29 * @param octets Data to count over
38 while (octets_len--) { in util_ones_count_get()
43 bite &= (bite - 1); in util_ones_count_get()
54 * - It shall have no more than six consecutive zeros or ones.
55 * - It shall not be the advertising channel packets' Access Address.
56 * - It shall not be a sequence that differs from the advertising channel
58 * - It shall not have all four octets equal.
59 * - It shall have no more than 24 transitions.
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| /Zephyr-latest/drivers/mdio/ |
| D | mdio_litex_liteeth.c | 4 * SPDX-License-Identifier: Apache-2.0
40 uint16_t data = 0; in mdio_litex_read() local
43 data <<= 1; in mdio_litex_read()
44 if (litex_read8(dev_cfg->r_addr) & LITEX_MDIO_DI) { in mdio_litex_read()
45 data |= 1; in mdio_litex_read()
47 litex_write8(LITEX_MDIO_CLK, dev_cfg->w_addr); in mdio_litex_read()
49 litex_write8(0, dev_cfg->w_addr); in mdio_litex_read()
53 LOG_DBG("Read data: 0x%04x", data); in mdio_litex_read()
55 *pdata = data; in mdio_litex_read()
58 static void mdio_litex_write(const struct mdio_litex_config *dev_cfg, uint32_t data, uint8_t len) in mdio_litex_write() argument
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| D | mdio_gpio.c | 4 * SPDX-License-Identifier: Apache-2.0
34 gpio_pin_set_dt(&dev_cfg->mdc_gpio, 1); in mdio_gpio_clock_the_bit()
36 gpio_pin_set_dt(&dev_cfg->mdc_gpio, 0); in mdio_gpio_clock_the_bit()
41 gpio_pin_configure_dt(&dev_cfg->mdio_gpio, dir ? GPIO_OUTPUT_ACTIVE : GPIO_INPUT); in mdio_gpio_dir()
49 uint16_t data = 0; in mdio_gpio_read() local
52 data <<= 1; in mdio_gpio_read()
54 if (gpio_pin_get_dt(&dev_cfg->mdio_gpio) == 1) { in mdio_gpio_read()
55 data |= 1; in mdio_gpio_read()
59 *pdata = data; in mdio_gpio_read()
63 uint32_t data, uint8_t len) in mdio_gpio_write() argument
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| /Zephyr-latest/tests/lib/net_buf/buf/src/ |
| D | main.c | 1 /* main.c - Application main entry point */
6 * SPDX-License-Identifier: Apache-2.0
77 struct net_buf_pool *pool = net_buf_pool_get(buf->pool_id); in buf_destroy()
86 struct net_buf_pool *pool = net_buf_pool_get(buf->pool_id); in fixed_destroy()
95 struct net_buf_pool *pool = net_buf_pool_get(buf->pool_id); in var_destroy()
136 for (i = 0; i < bufs_pool.buf_count - 1; i++) { in ZTEST()
137 frag->frags = net_buf_alloc_len(&bufs_pool, 74, K_NO_WAIT); in ZTEST()
138 zassert_not_null(frag->frags, "Failed to get fragment"); in ZTEST()
139 frag = frag->frags; in ZTEST()
187 for (i = 0; i < bufs_pool.buf_count - 1; i++) { in ZTEST()
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| /Zephyr-latest/dts/bindings/serial/ |
| D | uart-controller.yaml | 8 clock-frequency:
11 current-speed:
14 hw-flow-control:
23 - "none"
24 - "odd"
25 - "even"
26 stop-bits:
29 Sets the number of stop bits.
31 - "0_5"
32 - "1"
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| /Zephyr-latest/dts/bindings/dma/ |
| D | gd,gd32-dma-v1.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 channel: Select channel for data transmitting
12 - bit 6-7: Direction (see dma.h)
13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
18 - bit 9: Peripheral address increase
19 - 0x0: no address increment between transfers
20 - 0x1: increment address between transfers
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| D | andestech,atcdmac300.yaml | 4 # SPDX-License-Identifier: Apache-2.0
8 include: dma-controller.yaml
17 chain-transfer:
20 "#dma-cells":
23 dma-cells:
24 - channel
25 - slot
26 - channel-config
33 3. channel-config: A 32bit mask specifying the DMA channel configuration
35 -bit 0-1 : Direction (see dma.h)
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| D | gd,gd32-dma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 channel: Select channel for data transmitting
10 - bit 6-7: Direction (see dma.h)
11 - 0x0: MEMORY to MEMORY
12 - 0x1: MEMORY to PERIPH
13 - 0x2: PERIPH to MEMORY
14 - 0x3: reserved for PERIPH to PERIPH
16 - bit 9: Peripheral address increase
17 - 0x0: no address increment between transfers
18 - 0x1: increment address between transfers
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| D | st,stm32u5-dma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 DMA clients connected to the STM32 DMA controller must use a three-cell
17 dma-names = "tx", "rx";
20 1. channel: the stream or channel from 0 to (<dma-channels> - 1).
21 2. slot: DMA periph request ID, which is written in the REQSEL bits of the CxTR2
22 the slot is a value between <0> .. (<dma-requests> - 1).
23 3. channel-config: A 32bit mask specifying the DMA channel configuration
25 -bit 6-7 : Direction (see dma.h)
30 -bit 9 : Peripheral Increment Address
33 -bit 10 : Memory Increment Address
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_intel_vtd.c | 3 * SPDX-License-Identifier: Apache-2.0
86 struct vtd_ictl_data *data = dev->data; in vtd_flush_irte_from_cache() local
88 if (!data->pwc) { in vtd_flush_irte_from_cache()
89 cache_data_flush_range(&data->irte[irte_idx], in vtd_flush_irte_from_cache()
96 struct vtd_ictl_data *data = dev->data; in vtd_qi_init() local
100 data->qi_tail = 0; in vtd_qi_init()
102 value = VTD_IQA_REG_GEN_CONTENT((uintptr_t)data->qi, in vtd_qi_init()
111 struct vtd_ictl_data *data = dev->data; in vtd_qi_tail_inc() local
113 data->qi_tail += sizeof(struct qi_descriptor); in vtd_qi_tail_inc()
114 data->qi_tail %= (QI_NUM * sizeof(struct qi_descriptor)); in vtd_qi_tail_inc()
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | ist,tsic-xx6.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 https://www.ist-ag.com/sites/default/files/downloads/ATTSic_E.pdf
11 compatible = "ist,tsic-xx6";
13 data-bits = <14>;
14 lower-temperature-limit = <(-10)>;
15 higher-temperature-limit = <60>;
18 compatible: "ist,tsic-xx6"
23 type: phandle-array
26 lower-temperature-limit:
31 higher-temperature-limit:
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| /Zephyr-latest/drivers/spi/ |
| D | spi_bitbang.c | 2 * Copyright (c) 2021 Marc Reilly - Creative Product Design
4 * SPDX-License-Identifier: Apache-2.0
20 int bits; member
32 struct spi_bitbang_data *data, in spi_bitbang_configure() argument
35 if (config->operation & SPI_OP_MODE_SLAVE) { in spi_bitbang_configure()
37 return -ENOTSUP; in spi_bitbang_configure()
40 if (config->operation & (SPI_LINES_DUAL | SPI_LINES_QUAD | SPI_LINES_OCTAL)) { in spi_bitbang_configure()
42 return -ENOTSUP; in spi_bitbang_configure()
45 const int bits = SPI_WORD_SIZE_GET(config->operation); in spi_bitbang_configure() local
47 if (bits > 16) { in spi_bitbang_configure()
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| D | spi_rpi_pico_pio.c | 4 * SPDX-License-Identifier: Apache-2.0
52 uint32_t bits; member
56 /* ------------ */
58 /* ------------ */
71 /* ------------ */
73 /* ------------ */
88 /* ------------------- */
90 /* ------------------- */
105 /* ------------------------- */
107 /* ------------------------- */
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| /Zephyr-latest/drivers/serial/ |
| D | uart_sy1xx.c | 2 * SPDX-License-Identifier: Apache-2.0
22 uint8_t *data; member
58 struct sy1xx_uart_config *config = (struct sy1xx_uart_config *)dev->config; in sy1xx_uart_configure()
60 if (uart_cfg->baudrate == 0) { in sy1xx_uart_configure()
61 return -1; in sy1xx_uart_configure()
66 * and then will restart from 0, so we must give div - 1 as in sy1xx_uart_configure()
69 uint32_t divider = sy1xx_soc_get_peripheral_clock() / uart_cfg->baudrate - 1; in sy1xx_uart_configure()
75 * [3]: stop bits 0 = 1 stop bit in sy1xx_uart_configure()
76 * 1 = 2 stop bits in sy1xx_uart_configure()
77 * [2:1]: bits 00 = 5 bits in sy1xx_uart_configure()
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| D | uart_xlnx_ps.c | 1 /* uart_xlnx_ps.c - Xilinx Zynq family serial driver */
6 * SPDX-License-Identifier: Apache-2.0
19 * - the following macro for the number of bytes between register addresses:
41 /* For all register offsets and bits / bit masks:
42 * Comp. Xilinx Zynq-7000 Technical Reference Manual (ug585), chap. B.33
64 /* Control Register Bits Definition */
76 /* Mode Register Bits Definition */
84 #define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
85 #define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
87 #define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
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| /Zephyr-latest/include/zephyr/drivers/sip_svc/ |
| D | sip_svc_proto.h | 4 * SPDX-License-Identifier: Apache-2.0
15 * Client to fill in the input data in struct sip_svc_request format
61 * - Typical flow, synchronous request. Service expects EL3/EL2 firmware to
65 * - Asynchronous request. Service is required to poll the response via a
77 * - Successfully execute the request.
80 * - Unrecognized SMC/HVC Function ID.
83 * - The request is still in progress. Please try again.
86 * - The request have been rejected due to improper input data.
89 * - No response from target hardware yet.
92 * - Error occurred when executing the request.
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| /Zephyr-latest/drivers/i2c/ |
| D | i2c_dw.c | 1 /* dw_i2c.c - I2C file for Design Ware */
5 * Copyright (c) 2022 Andrei-Edward Popa
7 * SPDX-License-Identifier: Apache-2.0
49 #include "i2c-priv.h"
76 const struct i2c_dw_rom_config *const rom = dev->config; in cb_i2c_idma_transfer()
77 struct i2c_dw_dev_config *const dw = dev->data; in cb_i2c_idma_transfer()
79 dma_stop(rom->dma_dev, channel); in cb_i2c_idma_transfer()
83 dw->xfr_status = true; in cb_i2c_idma_transfer()
85 dw->xfr_status = false; in cb_i2c_idma_transfer()
94 write_rdlr(fifo_depth - 1, reg_base); in i2c_dw_set_fifo_th()
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_xlnx_ps_bank.c | 6 * SPDX-License-Identifier: Apache-2.0
24 #define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_bank_dev_cfg *)(_dev)->config)
25 #define DEV_DATA(_dev) ((struct gpio_xlnx_ps_bank_dev_data *const)(_dev)->data)
34 * - Pull up
35 * - Pull down
36 * - Open drain
37 * - Open source.
45 * -EINVAL if the specified pin index is out of range,
46 * -ENOTSUP if the pin configuration data contains a flag
64 return -ENOTSUP; in gpio_xlnx_ps_pin_configure()
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| /Zephyr-latest/tests/drivers/uart/uart_mix_fifo_poll/ |
| D | README.txt | 8 - main thread
9 - higher priority thread
10 - k_timer timeout context
12 From each context stream of data is being sent. Bytes in streams are encoded as
13 following: 4 MSB bits contains stream ID, 4 LSB bits are incremented.
16 UART receives loopback data and validates if for each stream (identified by ID)
17 data is consistent.
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| /Zephyr-latest/drivers/led_strip/ |
| D | tlc5971.c | 4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/led/led.h>
48 /** Length in bytes of data packet per TLC5791 device */
51 /** write command for writing control data and GS data to internal registers */
54 /** GS reference clock select bit in FC data (0 = internal oscillator clock, 1 = SCKI clock). */
57 /** GS reference clock edge select bit for OUTXn on-off timing control in FC data */
60 /** Constant-current output enable bit in FC data (0 = output control enabled, 1 = blank). */
63 /** Auto display repeat mode enable bit in FC data (0 = disabled, 1 = enabled). */
66 /** Display timing reset mode enable bit in FC data (0 = disabled, 1 = enabled). */
69 /** Bit mask for write cmd in data byte 27 */
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| /Zephyr-latest/drivers/fpga/ |
| D | fpga_altera_agilex_bridge.h | 4 * SPDX-License-Identifier: Apache-2.0
12 /* Mask for FPGA-HPS bridges */
82 * non-zero values indicate failure
85 /* indirect_bit - Field indicates an indirect command */
87 /* data_length - Field counts the number of word arguments which follow the
94 /* id - Field is returned unchanged from the matching command header and is
98 /* client_id - Field is returned unchanged from the matching command header and
110 /* update number bits */
112 /* minor acds release number bits */
114 /* major acds release number bits */
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