1 /* uart_xlnx_ps.c - Xilinx Zynq family serial driver */
6  * SPDX-License-Identifier: Apache-2.0
19  * - the following macro for the number of bytes between register addresses:
41 /* For all register offsets and bits / bit masks:
42  * Comp. Xilinx Zynq-7000 Technical Reference Manual (ug585), chap. B.33
64 /* Control Register Bits Definition */
76 /* Mode Register Bits Definition */
84 #define XUARTPS_MR_STOPMODE_2_BIT	0x00000080U /**< 2 stop bits */
85 #define XUARTPS_MR_STOPMODE_1_5_BIT	0x00000040U /**< 1.5 stop bits */
87 #define XUARTPS_MR_STOPMODE_SHIFT	6U  /**< Stop bits shift */
88 #define XUARTPS_MR_STOPMODE_MASK	0x000000A0U /**< Stop bits mask */
96 #define XUARTPS_MR_CHARLEN_6_BIT	0x00000006U /**< 6 bits data */
97 #define XUARTPS_MR_CHARLEN_7_BIT	0x00000004U /**< 7 bits data */
98 #define XUARTPS_MR_CHARLEN_8_BIT	0x00000000U /**< 8 bits data */
99 #define XUARTPS_MR_CHARLEN_SHIFT	1U  /**< Data Length shift */
100 #define XUARTPS_MR_CHARLEN_MASK		0x00000006U /**< Data length mask */
103 /* Interrupt Register Bits Definition */
120 /* Modem Control Register Bits Definition */
152 /** Device data structure */
169  * Writes 'Disable RX' and 'Disable TX' command bits into the respective
172  * While writing the disable command bits, the opposing enable command
173  * bits, which are set when enabling the UART, are cleared.
176  * of the UART are modified at run-time.
185 	/* Set control register bits [5]: TX_DIS and [3]: RX_DIS */  in xlnx_ps_disable_uart()
193  * Writes 'Enable RX' and 'Enable TX' command bits into the respective
196  * While writing the enable command bits, the opposing disable command
197  * bits, which are set when disabling the UART, are cleared.
200  * of the UART are being modified at run-time.
209 	/* Set control register bits [4]: TX_EN and [2]: RX_EN */  in xlnx_ps_enable_uart()
222  * registers is described in the Zynq-7000 TRM, chapter 19.2.3 'Baud Rate
230 	const struct uart_xlnx_ps_dev_config *dev_cfg = dev->config;  in set_baudrate()
231 	uint32_t baud = dev_cfg->baud_rate;  in set_baudrate()
232 	uint32_t clk_freq = dev_cfg->sys_clk_freq;  in set_baudrate()
253 				bauderr = baud - tmpbaud;  in set_baudrate()
255 				bauderr = tmpbaud - baud;  in set_baudrate()
264 		 * -> This function is always called from a context in which  in set_baudrate()
284 	const struct uart_xlnx_ps_dev_config *dev_cfg = dev->config;  in uart_xlnx_ps_init()
293 	/* Disable RX/TX before changing any configuration data */  in uart_xlnx_ps_init()
297 	err = pinctrl_apply_state(dev_cfg->pincfg, PINCTRL_STATE_DEFAULT);  in uart_xlnx_ps_init()
311 	/* Set RX FIFO trigger at 1 data bytes. */  in uart_xlnx_ps_init()
318 	set_baudrate(dev, dev_cfg->baud_rate);  in uart_xlnx_ps_init()
326 	dev_cfg->irq_config_func(dev);  in uart_xlnx_ps_init()
341  * @return 0 if a character arrived, -1 if the input buffer if empty.
352 		return -1;  in uart_xlnx_ps_poll_in()
360  * the data register.
395  * modified within this function come with the bits modified by
412 	 * bits [5..3] (PAR):  in uart_xlnx_ps_cfg2ll_parity()
450  * modified within this function come with the bits modified by
466 	 * bits [7..6] (NBSTOP):  in uart_xlnx_ps_cfg2ll_stopbits()
468 	 *  01b : 1.5 stop bits  in uart_xlnx_ps_cfg2ll_stopbits()
469 	 *  10b : 2 stop bits  in uart_xlnx_ps_cfg2ll_stopbits()
475 		/* Controller doesn't support 0.5 stop bits */  in uart_xlnx_ps_cfg2ll_stopbits()
493  * @brief Converts a data bit enum value to a Mode Register bit mask.
496  * framework for the configuration of the UART's data bit setting
500  * modified within this function come with the bits modified by
504  *                 the data bit configuration shall be added.
508  *         data bit configuration being provided by the caller.
515 	 * Translate the new data bit configuration to the mode register's  in uart_xlnx_ps_cfg2ll_databits()
516 	 * bits [2..1] (CHRL):  in uart_xlnx_ps_cfg2ll_databits()
517 	 *  0xb : 8 data bits  in uart_xlnx_ps_cfg2ll_databits()
518 	 *  10b : 7 data bits  in uart_xlnx_ps_cfg2ll_databits()
519 	 *  11b : 6 data bits  in uart_xlnx_ps_cfg2ll_databits()
525 		/* Controller doesn't support 5 or 9 data bits */  in uart_xlnx_ps_cfg2ll_databits()
551  * being modified within this function come with the bits modified
587  * @brief Configures the UART device at run-time.
589  * Configures the UART device at run-time according to the
590  * configuration data provided by the caller.
602 	(struct uart_xlnx_ps_dev_config *)dev->config;  in uart_xlnx_ps_configure()
612 	/* Mask out all items that might be re-configured */  in uart_xlnx_ps_configure()
619 	if ((!uart_xlnx_ps_cfg2ll_parity(&mode_reg, cfg->parity)) ||  in uart_xlnx_ps_configure()
620 		(!uart_xlnx_ps_cfg2ll_stopbits(&mode_reg, cfg->stop_bits)) ||  in uart_xlnx_ps_configure()
621 		(!uart_xlnx_ps_cfg2ll_databits(&mode_reg, cfg->data_bits)) ||  in uart_xlnx_ps_configure()
622 		(!uart_xlnx_ps_cfg2ll_hwctrl(&modemcr_reg, cfg->flow_ctrl))) {  in uart_xlnx_ps_configure()
623 		return -ENOTSUP;  in uart_xlnx_ps_configure()
630 	set_baudrate(dev, cfg->baudrate);  in uart_xlnx_ps_configure()
631 	dev_cfg->baud_rate = cfg->baudrate;  in uart_xlnx_ps_configure()
637 	/* Re-enable the controller */  in uart_xlnx_ps_configure()
663 	 * bits [5..3] (PAR):  in uart_xlnx_ps_ll2cfg_parity()
664 	 *  000b : even -> reset value  in uart_xlnx_ps_ll2cfg_parity()
705 	 * bits [7..6] (NBSTOP):  in uart_xlnx_ps_ll2cfg_stopbits()
706 	 *  00b : 1 stop bit -> reset value  in uart_xlnx_ps_ll2cfg_stopbits()
707 	 *  01b : 1.5 stop bits  in uart_xlnx_ps_ll2cfg_stopbits()
708 	 *  10b : 2 stop bits  in uart_xlnx_ps_ll2cfg_stopbits()
724  * @brief Converts a Mode Register bit mask to a data bit configuration
727  * Converts a bit mask representing the UART's data bit setting within
732  *                 data bit setting shall be extracted.
734  * @return The current data bit setting mapped to the UART driver API's
741 	 * Obtain the current data bit configuration from the mode register's  in uart_xlnx_ps_ll2cfg_databits()
742 	 * bits [2..1] (CHRL):  in uart_xlnx_ps_ll2cfg_databits()
743 	 *  0xb : 8 data bits -> reset value  in uart_xlnx_ps_ll2cfg_databits()
744 	 *  10b : 7 data bits  in uart_xlnx_ps_ll2cfg_databits()
745 	 *  11b : 6 data bits  in uart_xlnx_ps_ll2cfg_databits()
779 	 *  0b : no flow control -> reset value  in uart_xlnx_ps_ll2cfg_hwctrl()
793  * @brief Returns the current configuration of the UART at run-time.
795  * Returns the current configuration of the UART at run-time by obtaining
800  * @param cfg Pointer to the data structure to which the current configuration
808 	const struct uart_xlnx_ps_dev_config *dev_cfg = dev->config;  in uart_xlnx_ps_config_get()
812 	 * Read the Mode & Modem control registers - they contain  in uart_xlnx_ps_config_get()
813 	 * the current data / stop bit and parity settings (Mode  in uart_xlnx_ps_config_get()
820 	cfg->baudrate  = dev_cfg->baud_rate;  in uart_xlnx_ps_config_get()
821 	cfg->parity    = uart_xlnx_ps_ll2cfg_parity(mode_reg);  in uart_xlnx_ps_config_get()
822 	cfg->stop_bits = uart_xlnx_ps_ll2cfg_stopbits(mode_reg);  in uart_xlnx_ps_config_get()
823 	cfg->data_bits = uart_xlnx_ps_ll2cfg_databits(mode_reg);  in uart_xlnx_ps_config_get()
824 	cfg->flow_ctrl = uart_xlnx_ps_ll2cfg_hwctrl(modemcr_reg);  in uart_xlnx_ps_config_get()
833  * @brief Fill FIFO with data
836  * @param tx_data Data to transmit
849 	while (size--) {  in uart_xlnx_ps_fifo_fill()
860  * @brief Read data from FIFO
863  * @param rxData Data container
1076 	struct uart_xlnx_ps_dev_data_t *dev_data = dev->data;  in uart_xlnx_ps_irq_callback_set()
1078 	dev_data->user_cb = cb;  in uart_xlnx_ps_irq_callback_set()
1079 	dev_data->user_data = cb_data;  in uart_xlnx_ps_irq_callback_set()
1091 	const struct uart_xlnx_ps_dev_data_t *data = dev->data;  in uart_xlnx_ps_isr()  local
1093 	if (data->user_cb) {  in uart_xlnx_ps_isr()
1094 		data->user_cb(dev, data->user_data);  in uart_xlnx_ps_isr()