Lines Matching +full:data +full:- +full:bits

4  * SPDX-License-Identifier: Apache-2.0
40 uint16_t data = 0; in mdio_litex_read() local
43 data <<= 1; in mdio_litex_read()
44 if (litex_read8(dev_cfg->r_addr) & LITEX_MDIO_DI) { in mdio_litex_read()
45 data |= 1; in mdio_litex_read()
47 litex_write8(LITEX_MDIO_CLK, dev_cfg->w_addr); in mdio_litex_read()
49 litex_write8(0, dev_cfg->w_addr); in mdio_litex_read()
53 LOG_DBG("Read data: 0x%04x", data); in mdio_litex_read()
55 *pdata = data; in mdio_litex_read()
58 static void mdio_litex_write(const struct mdio_litex_config *dev_cfg, uint32_t data, uint8_t len) in mdio_litex_write() argument
60 uint32_t v_data = data; in mdio_litex_write()
63 LOG_DBG("Write data: 0x%08x", data); in mdio_litex_write()
65 v_data <<= 32 - v_len; in mdio_litex_write()
68 litex_write8(LITEX_MDIO_DO | LITEX_MDIO_OE, dev_cfg->w_addr); in mdio_litex_write()
71 dev_cfg->w_addr); in mdio_litex_write()
73 litex_write8(LITEX_MDIO_DO | LITEX_MDIO_OE, dev_cfg->w_addr); in mdio_litex_write()
75 litex_write8(LITEX_MDIO_OE, dev_cfg->w_addr); in mdio_litex_write()
77 litex_write8(LITEX_MDIO_CLK | LITEX_MDIO_OE, dev_cfg->w_addr); in mdio_litex_write()
79 litex_write8(LITEX_MDIO_OE, dev_cfg->w_addr); in mdio_litex_write()
82 v_len--; in mdio_litex_write()
89 litex_write8(LITEX_MDIO_CLK, dev_cfg->w_addr); in mdio_litex_turnaround()
91 litex_write8(0, dev_cfg->w_addr); in mdio_litex_turnaround()
93 litex_write8(LITEX_MDIO_CLK, dev_cfg->w_addr); in mdio_litex_turnaround()
95 litex_write8(0, dev_cfg->w_addr); in mdio_litex_turnaround()
101 const struct mdio_litex_config *const dev_cfg = dev->config; in mdio_litex_transfer()
102 struct mdio_litex_data *const dev_data = dev->data; in mdio_litex_transfer()
104 k_sem_take(&dev_data->sem, K_FOREVER); in mdio_litex_transfer()
106 litex_write8(LITEX_MDIO_OE, dev_cfg->w_addr); in mdio_litex_transfer()
107 /* PRE32: 32 bits '1' for sync*/ in mdio_litex_transfer()
109 /* ST: 2 bits start of frame */ in mdio_litex_transfer()
111 /* OP: 2 bits opcode, read '10' or write '01' */ in mdio_litex_transfer()
113 /* PA5: 5 bits PHY address */ in mdio_litex_transfer()
115 /* RA5: 5 bits register address */ in mdio_litex_transfer()
118 if (rw) { /* Write data */ in mdio_litex_transfer()
119 /* TA: 2 bits turn-around */ in mdio_litex_transfer()
122 } else { /* Read data */ in mdio_litex_transfer()
129 k_sem_give(&dev_data->sem); in mdio_litex_transfer()
135 uint16_t *data) in mdio_litex_read_mmi() argument
137 return mdio_litex_transfer(dev, prtad, devad, LITEX_MDIO_READ_OP, 0, data); in mdio_litex_read_mmi()
141 uint16_t data) in mdio_litex_write_mmi() argument
143 return mdio_litex_transfer(dev, prtad, devad, LITEX_MDIO_WRITE_OP, data, NULL); in mdio_litex_write_mmi()
148 struct mdio_litex_data *const dev_data = dev->data; in mdio_litex_initialize()
150 k_sem_init(&dev_data->sem, 1, 1); in mdio_litex_initialize()