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/Zephyr-latest/dts/bindings/spi/
Despressif,esp32-spi.yaml3 compatible: "espressif,esp32-spi"
5 include: [spi-controller.yaml, pinctrl-device.yaml]
11 pinctrl-0:
14 pinctrl-names:
17 half-duplex:
20 Enable half-duplex communication mode.
24 dummy-comp:
31 Enable 3-wire mode
35 dma-enabled:
39 dma-clk:
[all …]
/Zephyr-latest/dts/bindings/mtd/
Dnxp,imx-flexspi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: [spi-device.yaml, "jedec,jesd216.yaml"]
9 cs-interval-unit:
13 - 1
14 - 256
20 cs-interval:
28 cs-setup-time:
32 Chip select setup time, in serial clock cycles. See the TCSS field in
36 cs-hold-time:
40 Chip select hold time, in serial clock cycles. See the TCSH field in
[all …]
/Zephyr-latest/boards/nxp/mimxrt1050_evk/
Dmimxrt1050_evk_mimxrt1052_hyperflash.dts4 * SPDX-License-Identifier: Apache-2.0
11 zephyr,flash-controller = &s26ks512s0;
13 zephyr,code-partition = &slot0_partition;
19 ahb-prefetch;
20 ahb-read-addr-opt;
21 pinctrl-0 = <&pinmux_flexspi1>;
22 pinctrl-names = "default";
23 ahb-bufferable;
24 ahb-cacheable;
25 sck-differential-clock;
[all …]
/Zephyr-latest/boards/nxp/mimxrt1060_evk/
Dmimxrt1060_evk_mimxrt1062_hyperflash.dts4 * SPDX-License-Identifier: Apache-2.0
11 zephyr,flash-controller = &s26ks512s0;
13 zephyr,code-partition = &slot0_partition;
19 ahb-prefetch;
20 ahb-read-addr-opt;
21 ahb-bufferable;
22 ahb-cacheable;
23 sck-differential-clock;
24 combination-mode;
25 rx-clock-source = <3>;
[all …]
/Zephyr-latest/dts/bindings/qspi/
Dnxp,s32-qspi.yaml2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-qspi"
12 include: [base.yaml, pinctrl-device.yaml]
20 "#address-cells":
23 "#size-cells":
26 data-rate:
29 - SDR
30 - DDR
33 - Single Data Rate (SDR): sampling of incoming data occurs on single edges.
34 - Double Data Rate (DDR): sampling of incoming data occurs on both edges.
[all …]
/Zephyr-latest/dts/bindings/net/wireless/
Dnordic,nrf21540-fem.yaml2 # SPDX-License-Identifier: Apache-2.0
6 This is a representation of the nRF21540 Radio Front-End module.
8 See the "nordic,nrf21540-fem-spi" binding to configure the SPI
11 the FEM and SPI configurations using the spi-if property.
17 compatible = "nordic,nrf-spim";
19 cs-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
22 my_spi_if: nrf21540-spi@0 {
23 compatible = "nordic,nrf21540-fem-spi";
25 spi-max-frequency = <8000000>;
30 compatible = "nordic,nrf21540-fem";
[all …]
/Zephyr-latest/boards/nxp/frdm_rw612/
Dfrdm_rw612_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include "frdm_rw612-pinctrl.dtsi"
15 usart-0 = &flexcomm3;
16 i2c-0 = &flexcomm2;
17 pwm-0 = &sctimer;
24 zephyr,shell-uart = &flexcomm3;
28 compatible = "gpio-leds";
36 compatible = "nxp,lpc-usart";
38 current-speed = <115200>;
39 pinctrl-0 = <&pinmux_flexcomm3_usart>;
[all …]
/Zephyr-latest/boards/nxp/frdm_mcxn947/
Dfrdm_mcxn947.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include "frdm_mcxn947-pinctrl.dtsi"
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
19 mcuboot-button0 = &user_button_2;
23 compatible = "gpio-leds";
42 compatible = "gpio-keys";
58 * This node describes the GPIO pins of the LCD-PAR-S035 panel 8080 interface.
60 nxp_lcd_8080_connector: lcd-8080-connector {
61 compatible = "nxp,lcd-8080";
[all …]
/Zephyr-latest/boards/nxp/mimxrt1062_fmurt6/
Dmimxrt1062_fmurt6.dts2 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "mimxrt1062_fmurt6-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/pwm/pwm.h>
25 telem4-gps2 = &lpuart5;
29 zephyr,flash-controller = &s26ks512s0;
31 zephyr,code-partition = &slot0_partition;
32 zephyr,uart-mcumgr = &lpuart7;
37 zephyr,shell-uart = &lpuart7;
42 compatible = "gpio-leds";
[all …]
/Zephyr-latest/boards/nxp/rd_rw612_bga/
Drd_rw612_bga.dtsi2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include "rd_rw612_bga-pinctrl.dtsi"
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
16 usart-0 = &flexcomm3;
18 i2c-0 = &flexcomm2;
20 dmic-dev = &dmic0;
21 mcuboot-button0 = &sw_4;
22 pwm-0 = &sctimer;
28 zephyr,code-partition = &slot0_partition;
[all …]
/Zephyr-latest/soc/nxp/imxrt/
Dflexspi_nor_config.h6 * SPDX-License-Identifier: Apache-2.0
183 /* !< Switch to 0-4-4/0-8-8 mode */
196 /* !< [0x000-0x003] Tag, fixed value 0x42464346UL */
198 /* !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */
200 /* !< [0x008-0x00b] Reserved for future use */
202 /* !< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */
204 /* !< [0x00d-0x00d] CS hold time, default value: 3 */
206 /* !< [0x00e-0x00e] CS setup time, default value: 3 */
208 /* !< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For */
211 /* !< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */
[all …]
/Zephyr-latest/doc/build/dts/
Dbindings-upstream.rst1 .. _dt-writing-bindings:
21 Zephyr aims for devicetree :ref:`dt-source-compatibility`. Therefore, if there
24 justify any Zephyr-specific divergences.
28 - There is an existing binding in the mainline Linux kernel. See
32 - Your hardware vendor provides an official binding outside of the Linux
48 https://docs.kernel.org/devicetree/bindings/writing-bindings.html
55 - For example, a binding for compatible ``vnd,foo`` must be named ``vnd,foo.yaml``.
56 - If the binding is bus-specific, you can append the bus to the file name;
57 for example, if the binding YAML has ``on-bus: bar``, you may name the file
58 ``vnd,foo-bar.yaml``.
[all …]
/Zephyr-latest/drivers/bluetooth/hci/
Dapollox_blue.c4 * SPDX-License-Identifier: Apache-2.0
112 /* The CS pin is used to wake up the controller as well. If the controller is not ready in bt_apollo_controller_ready_wait()
113 * to receive the SPI packet, need to inactivate the CS at first and reconfigure the pin in bt_apollo_controller_ready_wait()
114 * to CS function again before next sending attempt. in bt_apollo_controller_ready_wait()
132 /* Give the controller some time to boot */ in bt_apollo_controller_reset()
139 int ret = -ENOTSUP; in bt_apollo_spi_send()
172 int ret = -ENOTSUP; in bt_apollo_spi_rcv()
180 ret = -1; in bt_apollo_spi_rcv()
192 if (!BLEIFn(0)->BSTATUS_b.BLEIRQ) { in bt_apollo_spi_rcv()
193 ret = -1; in bt_apollo_spi_rcv()
[all …]
Dhci_spi_st.c1 /* hci_spi_st.c - STMicroelectronics HCI SPI Bluetooth driver */
7 * SPDX-License-Identifier: Apache-2.0
65 #define MAX_MTU (SPI_MAX_MSG_LEN - H4_HDR_SIZE - BT_L2CAP_HDR_SIZE - BT_HCI_ACL_HDR_SIZE)
126 return -ENOTSUP; in bluenrg_bt_reset()
138 /* Give firmware some time to read the IRQ high */ in bluenrg_bt_reset()
210 /* On BlueNRG-MS, host is expected to read */
236 return -EINVAL; in bt_spi_get_header()
247 /* Make sure CS is raised before a new attempt */ in bt_spi_get_header()
248 gpio_pin_set_dt(&bus.config.cs.gpio, 0); in bt_spi_get_header()
257 attempts--; in bt_spi_get_header()
[all …]
/Zephyr-latest/drivers/adc/
Dadc_rpi_pico.c5 * SPDX-License-Identifier: Apache-2.0
27 #define ADC_RPI_CHANNEL_NUM (ADC_CS_RROBIN_MSB - ADC_CS_RROBIN_LSB + 1)
69 hw_set_bits(&adc_hw->cs, ADC_CS_START_ONCE_BITS); in adc_start_once()
74 return (uint16_t)adc_hw->result; in adc_get_result()
79 return (adc_hw->cs & ADC_CS_ERR_BITS) ? true : false; in adc_get_err()
85 hw_set_bits(&adc_hw->fcs, ADC_FCS_OVER_BITS); in adc_clear_errors()
86 hw_set_bits(&adc_hw->fcs, ADC_FCS_UNDER_BITS); in adc_clear_errors()
87 hw_set_bits(&adc_hw->fcs, ADC_FCS_ERR_BITS); in adc_clear_errors()
88 hw_set_bits(&adc_hw->cs, ADC_CS_ERR_STICKY_BITS); in adc_clear_errors()
93 adc_hw->cs = ADC_CS_EN_BITS; in adc_enable()
[all …]
/Zephyr-latest/include/zephyr/drivers/
Dspi.h4 * SPDX-License-Identifier: Apache-2.0
27 #include <zephyr/dt-bindings/spi/spi.h>
73 * Whatever data is transmitted is looped-back to the receiving buffer of
115 /** Requests - if possible - to keep CS asserted after the transaction */
124 /** Active high logic on CS. Usually, and by default, CS logic is active
128 * the CS control to a gpio line through struct spi_cs_control would be
139 * Default is single, which is the case most of the time.
155 * This can be used to control a CS line via a GPIO line, instead of
156 * using the controller inner CS logic.
161 * GPIO devicetree specification of CS GPIO.
[all …]
/Zephyr-latest/boards/nxp/mimxrt595_evk/
Dmimxrt595_evk_mimxrt595s_cm33.dts2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include "mimxrt595_evk_mimxrt595s_cm33-pinctrl.dtsi"
16 model = "NXP MIMXRT595-EVK board";
25 usart-0 = &flexcomm0;
30 pwm-0 = &sc_timer;
31 dmic-dev = &dmic0;
32 mcuboot-button0 = &user_button_1;
[all …]
/Zephyr-latest/tests/boards/mec172xevb_assy6906/qspi/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
30 * bits[15:8] = bytes number of clocks with data lines tri-stated
88 * mode = 1(full-duplex), 2(dual), 4(quad)
89 * full-duplex: 8 clocks per byte
113 return -EINVAL; in spi_flash_address_format()
117 dest[i] = (uint8_t)((spi_addr >> ((addrsz - (i + 1U)) * 8U)) & 0xffU); in spi_flash_address_format()
210 * - Find spi device
211 * - Read flash jedec id
248 * - write enable
249 * - erase data in flash device
[all …]
/Zephyr-latest/drivers/espi/
Despi_saf_mchp_xec_v2.c5 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
27 /* SAF EC Portal read/write flash access limited to 1-64 bytes */
61 * Delay before first Poll-1 command after suspend in 20 ns units
62 * Hold off suspend for this interval if erase or program in 32KHz periods.
96 static inline void mchp_saf_cs_descr_wr(struct mchp_espi_saf *regs, uint8_t cs, in mchp_saf_cs_descr_wr() argument
99 regs->SAF_CS_OP[cs].OP_DESCR = val; in mchp_saf_cs_descr_wr()
102 static inline void mchp_saf_poll2_mask_wr(struct mchp_espi_saf *regs, uint8_t cs, in mchp_saf_poll2_mask_wr() argument
105 LOG_DBG("%s cs: %d mask %x", __func__, cs, val); in mchp_saf_poll2_mask_wr()
106 if (cs == 0) { in mchp_saf_poll2_mask_wr()
[all …]
Despi_saf_mchp_xec.c5 * SPDX-License-Identifier: Apache-2.0
20 /* SAF EC Portal read/write flash access limited to 1-64 bytes */
44 * Delay before first Poll-1 command after suspend in 20 ns units
45 * Hold off suspend for this interval if erase or program in 32KHz periods.
72 static inline void mchp_saf_cs_descr_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs, in mchp_saf_cs_descr_wr() argument
75 regs->SAF_CS_OP[cs].OP_DESCR = val; in mchp_saf_cs_descr_wr()
78 static inline void mchp_saf_poll2_mask_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs, in mchp_saf_poll2_mask_wr() argument
81 LOG_DBG("%s cs: %d mask %x", __func__, cs, val); in mchp_saf_poll2_mask_wr()
82 if (cs == 0) { in mchp_saf_poll2_mask_wr()
83 regs->SAF_CS0_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
[all …]
/Zephyr-latest/drivers/flash/
Dspi_nor.c2 * Copyright (c) 2018 Savoir-Faire Linux.
8 * SPDX-License-Identifier: Apache-2.0
36 * * Some devices support a Deep Power-Down mode which reduces current
41 * * PM_DEVICE_STATE_SUSPENDED corresponds to deep-power-down mode;
63 #define DEV_CFG(_dev_) ((const struct spi_nor_config * const) (_dev_)->config)
66 /* MXICY Low-power/high perf mode is second bit in configuration register 2 */
72 /* Build-time data associated with the device. */
92 /* Expected JEDEC ID, from jedec-id property */
96 /* Optional support for entering 32-bit address mode. */
101 /* Length of BFP structure, in 32-bit words. */
[all …]
/Zephyr-latest/drivers/spi/
Dspi_dw.c6 * SPDX-License-Identifier: Apache-2.0
11 /* spi_dw.c - Designware SPI driver implementation */
47 spi_context_is_slave(&spi->ctx)); in spi_dw_is_slave()
52 struct spi_dw_data *spi = dev->data; in completed()
53 struct spi_context *ctx = &spi->ctx; in completed()
59 if (spi_context_tx_on(&spi->ctx) || in completed()
60 spi_context_rx_on(&spi->ctx)) { in completed()
65 /* need to give time for FIFOs to drain before issuing more commands */ in completed()
75 if (spi_cs_is_gpio(ctx->config)) { in completed()
85 spi_context_complete(&spi->ctx, dev, error); in completed()
[all …]
Dspi_xec_qmspi_ldma.c4 * SPDX-License-Identifier: Apache-2.0
20 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
21 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
35 * data bytes will be left shifted by 1. Work-around for SPI Mode 3 is
94 /* Device run time data */
123 return -ETIMEDOUT; in xec_qmspi_spin_yield()
133 * Some QMSPI timing register may be modified by the Boot-ROM OTP
144 taps[0] = regs->TM_TAPS; in qmspi_reset()
145 taps[1] = regs->TM_TAPS_ADJ; in qmspi_reset()
146 taps[2] = regs->TM_TAPS_CTRL; in qmspi_reset()
[all …]
Dspi_pw.c3 * SPDX-License-Identifier: Apache-2.0
47 return spi_context_tx_on(&spi->ctx) || spi_context_rx_on(&spi->ctx); in is_spi_transfer_ongoing()
132 uint8_t dfs = SPI_WORD_SIZE_GET(config->operation); in spi_pw_get_frame_size()
137 LOG_WRN("Unsupported dfs, 1-byte size will be used"); in spi_pw_get_frame_size()
146 struct spi_pw_data *spi = dev->data; in spi_pw_cs_ctrl_enable()
149 if (spi->cs_mode == CS_SW_MODE) { in spi_pw_cs_ctrl_enable()
151 } else if (spi->cs_mode == CS_GPIO_MODE) { in spi_pw_cs_ctrl_enable()
152 spi_context_cs_control(&spi->ctx, true); in spi_pw_cs_ctrl_enable()
155 if (spi->cs_mode == CS_SW_MODE) { in spi_pw_cs_ctrl_enable()
157 } else if (spi->cs_mode == CS_GPIO_MODE) { in spi_pw_cs_ctrl_enable()
[all …]
/Zephyr-latest/samples/drivers/espi/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
222 spi_cfg.cs.delay = 0; in spi_saf_init()
223 spi_cfg.cs.gpio.pin = 0; in spi_saf_init()
224 spi_cfg.cs.gpio.dt_flags = 0; in spi_saf_init()
225 spi_cfg.cs.gpio.port = NULL; in spi_saf_init()
249 return -1; in spi_saf_init()
280 * SAF test requires SPI flash quad enabled so the WP#/HOLD# signals in spi_saf_init()
395 return -1; in spi_saf_init()
427 limit = pr->start + pr->size - 1U; in pr_check_range()
430 if (regs->SAF_PROT_RG[pr->pr_num].START != (pr->start >> 12)) { in pr_check_range()
[all …]

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