| /Zephyr-latest/kernel/ |
| D | Kconfig.obj_core | 5 bool "Object core framework"
8 This option enables the object core framework. This will link
16 bool "Integrate condition variables into object core framework"
20 object core framework.
23 bool "Integrate events into object core framework"
27 core framework.
30 bool "Integrate FIFOs into object core framework"
33 When enabled, this option integrates FIFOs into the object core
37 bool "Integrate LIFOs into object core framework"
40 When enabled, this option integrates LIFOs into the object core
[all …]
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| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_intel_adsp.h | 12 * Get register offset for core
18 * DSP Core Watch Dog Timer Control & Status
23 * This register controls the DSP Core watch dog timer policy.
49 * When set, it allow the DSP Core reset to take place upon second time out of the
56 * DSP Core Watch Dog Timer IP Pointer
61 * This register provides the pointer to the DSP Core watch dog timer IP registers.
87 * @param core Core ID
89 static inline void intel_adsp_wdt_pause(uint32_t base, const uint32_t core) in intel_adsp_wdt_pause() argument
91 const uint32_t reg_addr = base + DSPCxWDTCS + DSPBRx_OFFSET(core); in intel_adsp_wdt_pause()
106 * @param core Core ID
[all …]
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| /Zephyr-latest/soc/nxp/imxrt/imxrt5xx/f1/include/ |
| D | _soc_inthandlers.h | 6 #include <xtensa/config/core-isa.h>
11 #error core-isa.h interrupt level does not match dispatcher!
14 #error core-isa.h interrupt level does not match dispatcher!
17 #error core-isa.h interrupt level does not match dispatcher!
20 #error core-isa.h interrupt level does not match dispatcher!
23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
[all …]
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| /Zephyr-latest/samples/boards/nordic/coresight_stm/pytest/ |
| D | test_stm.py | 53 def _check_benchmark_results(output: str, core: str) -> None:
56 Search for benchmark results related to 'core' coprocessor.
60 rf"{core}: Timing for log message with 0 arguments: (.+)us", output
65 rf"{core}: Timing for log message with 1 argument: (.+)us", output
70 rf"{core}: Timing for log message with 2 arguments: (.+)us", output
75 rf"{core}: Timing for log message with 3 arguments: (.+)us", output
80 rf"{core}: Timing for log_message with string: (.+)us", output
85 rf"{core}: Timing for tracepoint: (.+)us", output
90 rf"{core}: Timing for tracepoint_d32: (.+)us", output
156 STM proxy (Application core) decodes logs from all domains.
[all …]
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| /Zephyr-latest/soc/nxp/imx/imx8x/adsp/ |
| D | _soc_inthandlers.h | 18 #include <xtensa/config/core-isa.h>
23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
38 #error core-isa.h interrupt level does not match dispatcher!
41 #error core-isa.h interrupt level does not match dispatcher!
44 #error core-isa.h interrupt level does not match dispatcher!
47 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-latest/soc/nxp/imx/imx8/adsp/ |
| D | _soc_inthandlers.h | 18 #include <xtensa/config/core-isa.h>
23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
38 #error core-isa.h interrupt level does not match dispatcher!
41 #error core-isa.h interrupt level does not match dispatcher!
44 #error core-isa.h interrupt level does not match dispatcher!
47 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-latest/soc/nxp/imx/imx8m/adsp/ |
| D | _soc_inthandlers.h | 18 #include <xtensa/config/core-isa.h>
23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
38 #error core-isa.h interrupt level does not match dispatcher!
41 #error core-isa.h interrupt level does not match dispatcher!
44 #error core-isa.h interrupt level does not match dispatcher!
47 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-latest/samples/subsys/ipc/rpmsg_service/ |
| D | README.rst | 14 perspective and code. Note that the remote and primary image core images can be
59 Master core received a message: 1
60 Master core received a message: 3
61 Master core received a message: 5
63 Master core received a message: 99
73 Remote core received a message: 0
74 Remote core received a message: 2
75 Remote core received a message: 4
77 Remote core received a message: 98
102 and network core images, the following messages (one for master and one for
[all …]
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| /Zephyr-latest/tests/ztest/fail/ |
| D | CMakeLists.txt | 10 # Set the target binary for the 'core' external project. The path to this must match the one set
12 add_compile_definitions(FAIL_TARGET_BINARY="${CMAKE_BINARY_DIR}/core/bin/testbinary")
16 # Set the target binary for the 'core' external project. The path to this must match the one set
18 add_compile_definitions(FAIL_TARGET_BINARY="${CMAKE_BINARY_DIR}/core/bin/zephyr.exe")
27 # 'core' project as a cmake argument.
35 # Add the 'core' external project which will mirror the configs of this project.
36 ExternalProject_Add(core
37 SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}/core
40 -DCMAKE_INSTALL_PREFIX:PATH=${CMAKE_BINARY_DIR}/core
43 add_dependencies(${target} core)
|
| /Zephyr-latest/tests/boards/nrf/coresight_stm/pytest/ |
| D | test_stm.py | 68 def _check_benchmark_results(output: str, core: str, constraints: STMLimits) -> None:
71 Search for benchmark results related to 'core' coprocessor.
77 "regex": rf"{core}: Timing for log message with 0 arguments: (.+)us",
81 "regex": rf"{core}: Timing for log message with 1 argument: (.+)us",
85 "regex": rf"{core}: Timing for log message with 2 arguments: (.+)us",
89 "regex": rf"{core}: Timing for log message with 3 arguments: (.+)us",
93 "regex": rf"{core}: Timing for log_message with string: (.+)us",
97 "regex": rf"{core}: Timing for tracepoint: (.+)us",
101 "regex": rf"{core}: Timing for tracepoint_d32: (.+)us",
114 ), f"{core}: Timing for {check} - {observed} us exceeds {threshold} us"
[all …]
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| /Zephyr-latest/soc/nxp/imx/imx8ulp/adsp/ |
| D | _soc_inthandlers.h | 18 #include <xtensa/config/core-isa.h>
23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
38 #error core-isa.h interrupt level does not match dispatcher!
41 #error core-isa.h interrupt level does not match dispatcher!
44 #error core-isa.h interrupt level does not match dispatcher!
47 #error core-isa.h interrupt level does not match dispatcher!
[all …]
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| /Zephyr-latest/soc/nxp/imx/imx6sx/ |
| D | soc.c | 18 /* Move M4 core to the configured RDC domain */ in SOC_RdcInit()
21 /* Set access to WDOG3 for M4 core */ in SOC_RdcInit()
27 /* Set access to UART_1 for M4 core */ in SOC_RdcInit()
31 /* Set access to UART_2 for M4 core */ in SOC_RdcInit()
35 /* Set access to UART_3 for M4 core */ in SOC_RdcInit()
39 /* Set access to UART_4 for M4 core */ in SOC_RdcInit()
43 /* Set access to UART_5 for M4 core */ in SOC_RdcInit()
47 /* Set access to UART_6 for M4 core */ in SOC_RdcInit()
51 /* Set access to GPIO_1 for M4 core */ in SOC_RdcInit()
55 /* Set access to GPIO_2 for M4 core */ in SOC_RdcInit()
[all …]
|
| /Zephyr-latest/soc/espressif/common/include/ |
| D | _soc_inthandlers.h | 19 #include <xtensa/config/core-isa.h>
24 #error core-isa.h interrupt level does not match dispatcher!
27 #error core-isa.h interrupt level does not match dispatcher!
30 #error core-isa.h interrupt level does not match dispatcher!
33 #error core-isa.h interrupt level does not match dispatcher!
36 #error core-isa.h interrupt level does not match dispatcher!
39 #error core-isa.h interrupt level does not match dispatcher!
42 #error core-isa.h interrupt level does not match dispatcher!
45 #error core-isa.h interrupt level does not match dispatcher!
48 #error core-isa.h interrupt level does not match dispatcher!
[all …]
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| /Zephyr-latest/samples/boards/nordic/nrf53_sync_rtc/ |
| D | README.rst | 4 Synchronize system and network core RTC clocks.
10 core are synchronized. The result of synchronization is an offset value on network
11 core which can be applied to the system tick for logging timestamping.
14 both cores. Application core periodically reads current system tick and stores it in
16 core. In the context of the IPC interrupt handler, network core is logging timestamp
19 and once procedure is completed timestamps are synchronized. Network core timestamp
63 [00:00:00.054,534] <inf> main: Local timestamp: 1787, application core timestamp: 10056
64 [00:00:00.104,553] <inf> main: Local timestamp: 3426, application core timestamp: 11695
65 [00:00:00.154,571] <inf> main: Local timestamp: 5065, application core timestamp: 13334
66 [00:00:00.204,589] <inf> main: Local timestamp: 6704, application core timestamp: 14973
[all …]
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| /Zephyr-latest/dts/bindings/mbox/ |
| D | nxp,s32-mru.yaml | 10 core.
19 In a normal use-case for IPC, the receiver core must enable and set the number
20 of receive channels on the MRU instance coupled with the core, for instance in
25 For example, core B and C want to send messages to core A in channels 0 and 1,
28 // overlay of core A
34 // overlays of core B and core C
53 It should be set by the receiver core coupled with this MRU instance.
|
| /Zephyr-latest/soc/intel/intel_adsp/common/include/ |
| D | cavs-idc.h | 16 * Each core has a set of registers its is supposed to use, but all
20 * Each core has a "ITC" register associated with each other core in
22 * ITC register, an IDC interrupt is latched for the target core.
26 * On the target core, there is a "TFC" register for each core that
40 * So you can send a synchronous message from core "src" (where src is
42 * core "dst" with:
44 * IDC[src].core[dst].itc = BIT(31) | message;
45 * while (IDC[src].core[dst].itc & BIT(31)) {}
50 * uint32_t my_msg = IDC[dst].core[src].tfc & 0x7fffffff;
51 * IDC[dst].core[src].tfc = BIT(31); // clear high bit to signal completion
[all …]
|
| /Zephyr-latest/dts/bindings/gpio/ |
| D | nordic,nrf-gpio-forwarder.yaml | 8 the application core to the network core if the latter should drive them.
10 nRF53 application core should forward to the nRF53 network core.
13 core is responsible for configuring the pins and driving them as needed.
17 present in DTS file targeted for the nRF5340 network core, which defines
29 network core, all the GPIO pins used to control it must be forwarded by
30 the nRF5340 application core to the network core. Consider the following
32 application core:
42 control over the following GPIO pins to the network core:
|
| /Zephyr-latest/soc/cdns/sample_controller32/include/ |
| D | _soc_inthandlers.h | 19 #include <xtensa/config/core-isa.h>
24 #error core-isa.h interrupt level does not match dispatcher!
27 #error core-isa.h interrupt level does not match dispatcher!
30 #error core-isa.h interrupt level does not match dispatcher!
33 #error core-isa.h interrupt level does not match dispatcher!
36 #error core-isa.h interrupt level does not match dispatcher!
39 #error core-isa.h interrupt level does not match dispatcher!
42 #error core-isa.h interrupt level does not match dispatcher!
45 #error core-isa.h interrupt level does not match dispatcher!
48 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-latest/soc/intel/intel_adsp/cavs/ |
| D | _soc_inthandlers.h | 17 #include <xtensa/config/core-isa.h>
22 #error core-isa.h interrupt level does not match dispatcher!
25 #error core-isa.h interrupt level does not match dispatcher!
28 #error core-isa.h interrupt level does not match dispatcher!
31 #error core-isa.h interrupt level does not match dispatcher!
34 #error core-isa.h interrupt level does not match dispatcher!
37 #error core-isa.h interrupt level does not match dispatcher!
40 #error core-isa.h interrupt level does not match dispatcher!
43 #error core-isa.h interrupt level does not match dispatcher!
46 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| D | multiprocessing.c | 20 (0x2 << 0)) /* "Core wake version" = 2 */
30 * could have come from any core, clear all of them. in soc_mp_startup()
35 IDC[cpu].core[i].tfc = BIT(31); in soc_mp_startup()
38 /* Interrupt must be enabled while running on current core */ in soc_mp_startup()
47 /* On cAVS v2.5, MP startup works differently. The core has in soc_start_core()
83 * whether the core is being turned on again or for the first time. in soc_start_core()
98 * be, so by default a core will launch successfully but then in soc_start_core()
115 /* Send power-up message to the other core. Start address in soc_start_core()
122 IDC[curr_cpu].core[cpu_num].ietc = ietc; in soc_start_core()
123 IDC[curr_cpu].core[cpu_num].itc = IDC_MSG_POWER_UP; in soc_start_core()
[all …]
|
| /Zephyr-latest/soc/nxp/lpc/lpc54xxx/gcc/ |
| D | startup_LPC54114_cm4.S | 32 /* Both the M0+ and M4 core come via this shared startup code,
33 * but the M0+ and M4 core have different vector tables.
34 * Determine if the core executing this code is the master or
35 * the slave and handle each core state individually. */
40 /* Flag for slave core (0) */
47 /* Determine which core (M0+ or M4) this code is running on */
48 /* r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) */
56 cmp r3, r2 /* Core ID matches M4 identifier */
58 mov r4, r5 /* Set flag for master core (1) */
60 /* Determine if M4 core is the master or slave */
[all …]
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| /Zephyr-latest/subsys/debug/coredump/ |
| D | Kconfig | 5 bool "Core Dump"
8 Enable core dump so it can be used for offline debugging.
20 Core dump is done via logging subsystem.
28 Core dump is saved to a flash partition with DTS alias
35 Core dump is done via memory window slot[1].
42 Core dump is done via custom mechanism defined out of tree
59 minimum core dump.
107 Core dump will contain the threads metadata section containing
|
| /Zephyr-latest/samples/net/cloud/aws_iot_mqtt/ |
| D | README.rst | 2 :name: AWS IoT Core MQTT
5 Connect to AWS IoT Core and publish messages using MQTT.
11 can publish messages to AWS IoT Core using the MQTT protocol. Key features include:
15 - Establishing a TLS 1.2 connection with AWS IoT Core servers
16 - Subscribing to a topic on AWS IoT Core
17 - Publishing data to AWS IoT Core
26 - An AWS account with access to AWS IoT Core
35 authenticate to the AWS IoT Core. The sample includes a script to convert
38 Register a *thing* in AWS IoT Core and download the certificate and private key.
44 Core region, thing, and device advisor configuration:
[all …]
|
| /Zephyr-latest/arch/arc/core/ |
| D | smp.c | 28 * arc_cpu_wake_flag is used to sync up master core and slave cores
29 * Slave core will spin for arc_cpu_wake_flag until master core sets
30 * it to the core id of slave core. Then, slave core clears it to notify
31 * master core that it's waken
80 * ARC_CONNECT_CMD_DEBUG_MASK_H: Core global halt. in arc_connect_debug_mask_update()
104 /* configure inter-core debug unit if available */ in arch_secondary_cpu_init()
146 * if the target is current core, hardware will ignore it in arch_sched_directed_ipi()
165 /* necessary master core init */ in arch_smp_init()
171 /* configure inter-core debug unit if available */ in arch_smp_init()
176 /* register ici interrupt, just need master core to register once */ in arch_smp_init()
[all …]
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| /Zephyr-latest/soc/openisa/rv32m1/ |
| D | Kconfig.soc | 8 this option to target the RI5CY or ZERO-RISCY core. This
9 option should not be used to target either Arm core.
15 OpenISA RV32M1 RI5CY core
21 OpenISA RV32M1 ZERO-RISCY core
|
