12  * Get register offset for core
18  * DSP Core Watch Dog Timer Control & Status
23  * This register controls the DSP Core watch dog timer policy.
49  * When set, it allow the DSP Core reset to take place upon second time out of the
56  * DSP Core Watch Dog Timer IP Pointer
61  * This register provides the pointer to the DSP Core watch dog timer IP registers.
87  * @param core Core ID
89 static inline void intel_adsp_wdt_pause(uint32_t base, const uint32_t core)  in intel_adsp_wdt_pause()  argument
91 	const uint32_t reg_addr = base + DSPCxWDTCS + DSPBRx_OFFSET(core);  in intel_adsp_wdt_pause()
106  * @param core Core ID
108 static inline void intel_adsp_wdt_resume(uint32_t base, const uint32_t core)  in intel_adsp_wdt_resume()  argument
110 	const uint32_t reg_addr = base + DSPCxWDTCS + DSPBRx_OFFSET(core);  in intel_adsp_wdt_resume()
122  * When set, it allow the DSP Core reset to take place upon second time out of the watchdog timer.
125  * @param core Core ID
127 static inline void intel_adsp_wdt_reset_set(uint32_t base, const uint32_t core, const bool enable)  in intel_adsp_wdt_reset_set()  argument
129 	sys_write32(enable ? DSPCxWDTCS_STORE : 0, base + DSPCxWDTCS + DSPBRx_OFFSET(core));  in intel_adsp_wdt_reset_set()
136  * When set, it allow the DSP Core reset to take place upon second time out of the
142  * @brief Get watchdog IP pointer for specified core.
147  * @param core Core ID
149 static inline uint32_t intel_adsp_wdt_pointer_get(uint32_t base, const uint32_t core)  in intel_adsp_wdt_pointer_get()  argument
151 	return FIELD_GET(DSPCxWDTIPPTR_PTR, sys_read32(base + DSPCxWDTIPPTR + DSPBRx_OFFSET(core)));  in intel_adsp_wdt_pointer_get()
160  * @param core Core ID
162 static inline uint32_t intel_adsp_wdt_version_get(uint32_t base, const uint32_t core)  in intel_adsp_wdt_version_get()  argument
164 	return FIELD_GET(DSPCxWDTIPPTR_VER, sys_read32(base + DSPCxWDTIPPTR + DSPBRx_OFFSET(core)));  in intel_adsp_wdt_version_get()