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/Zephyr-latest/dts/bindings/clock/
Dlitex,clkout.yaml2 # SPDX-License-Identifier: Apache-2.0
7 LiteX Mixed Mode Clock Manager clock output binding
13 "#clock-cells":
17 Number of cells in a clock specifier;
18 Typically 0 for nodes with a single clock output
19 and 1 for nodes with multiple clock outputs.
22 clock-output-names:
26 string of clock output signal name.
28 litex,clock-frequency:
32 default frequency in Hz for clock output
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Dlitex,clk.yaml2 # SPDX-License-Identifier: Apache-2.0
4 include: [clock-controller.yaml, base.yaml]
7 LiteX Mixed Mode Clock Manager
8 Common clock driver with MMCM unit for dynamic reconfiguration
9 of up to 7 clock outputs with ability to change frequency, duty
14 clock-cells:
15 - id
22 "#clock-cells":
26 clock-output-names:
28 type: string-array
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/Zephyr-latest/subsys/bluetooth/controller/ll_sw/openisa/lll/
Dlll_vendor.h2 * Copyright (c) 2018-2019 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
12 /* Worst-case time margin needed after event end-time in the air
13 * (done/preempt race margin + power-down/chain delay)
17 /* Ticker resolution margin
20 * clock.
28 /* TODO - fix up numbers re. HW */
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/nordic/lll/
Dlll_vendor.h2 * Copyright (c) 2018-2019 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
42 /* Worst-case time margin needed after event end-time in the air
43 * (done/preempt race margin + power-down/chain delay)
47 /* Sleep Clock Accuracy */
50 /* Inter-Event Space (IES) */
53 /* Ticker resolution margin
56 * clock.
68 * slow clock, the conservative approach was taken to use IFS value for all
73 /* Sub-microsecond conversion macros. With current timer resolution of ~30 us
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/Zephyr-latest/dts/riscv/
Driscv32-litex-vexriscv.dtsi2 * Copyright (c) 2018 - 2020 Antmicro <www.antmicro.com>
4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
12 compatible = "litex,vexriscv", "litex-dev";
21 #address-cells = <1>;
22 #size-cells = <0>;
24 clock-frequency = <100000000>;
25 compatible = "litex,vexriscv-standard", "riscv";
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/Zephyr-latest/boards/nxp/frdm_mcxa156/
Dboard.c3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
12 /* Core clock frequency: 150MHz */
15 /* System clock frequency. */
34 FMU0->FCTRL = in frdm_mcxa156_init()
35 (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); in frdm_mcxa156_init()
36 /* Specifies the operating voltage for the SRAM's read/write timing margin */ in frdm_mcxa156_init()
44 CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ in frdm_mcxa156_init()
51 FMU0->FCTRL = in frdm_mcxa156_init()
52 (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); in frdm_mcxa156_init()
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/Zephyr-latest/soc/st/stm32/stm32f4x/
Dpower.c4 * SPDX-License-Identifier: Apache-2.0
37 * low-power mode takes typically 8us, max 13us more time than with the main in pm_state_set()
39 * It means we have to add significant margin to the exit-latency anyway, in pm_state_set()
40 * so it is worth always using the low-power regulator. in pm_state_set()
63 /* Restore the clock setup. */ in pm_state_exit_post_ops()
67 LOG_DBG("Unsupported power substate-id %u", state); in pm_state_exit_post_ops()
80 /* Enable Power clock. It should by done by default, but make sure to in stm32_power_init()
/Zephyr-latest/tests/drivers/can/timing/src/
Dmain.c2 * Copyright (c) 2022-2024 Vestas Wind Systems A/S
5 * SPDX-License-Identifier: Apache-2.0
20 * @brief Allowed sample point calculation margin in permille.
55 /* CiA 601-2 recommended data phase bitrates */
78 const uint32_t ts = 1 + timing->prop_seg + timing->phase_seg1 + timing->phase_seg2; in assert_bitrate_correct()
83 zassert_not_equal(timing->prescaler, 0, "prescaler is zero"); in assert_bitrate_correct()
86 zassert_equal(err, 0, "failed to get core CAN clock"); in assert_bitrate_correct()
88 bitrate_calc = core_clock / timing->prescaler / ts; in assert_bitrate_correct()
105 zassert_true(timing->sjw <= max->sjw, "sjw exceeds max"); in assert_timing_within_bounds()
106 zassert_true(timing->prop_seg <= max->prop_seg, "prop_seg exceeds max"); in assert_timing_within_bounds()
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/Zephyr-latest/drivers/clock_control/
Dclock_control_litex.h4 * SPDX-License-Identifier: Apache-2.0
64 lcko = &ldev->clkouts[N]; \
65 lcko->id = CLKOUT_ID(N); \
67 lcko->clkout_div = clkout_div; \
68 lcko->def.freq = CLKOUT_FREQ(N); \
69 lcko->def.phase = CLKOUT_PHASE(N); \
70 lcko->def.duty.num = CLKOUT_DUTY_NUM(N); \
71 lcko->def.duty.den = CLKOUT_DUTY_DEN(N); \
72 lcko->margin.m = CLKOUT_MARGIN(N); \
73 lcko->margin.exp = CLKOUT_MARGIN_EXP(N);
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Dclock_control_litex.c4 * SPDX-License-Identifier: Apache-2.0
66 …* https://github.com/Digilent/Zybo-hdmi-out/blob/b991fff6e964420ae3c00c3dbee52f2ad748b3ba/sdk/disp…
213 return litex_clk_filter_table[glob_mul - 1]; in litex_clk_lookup_filter()
219 return litex_clk_lock_table[glob_mul - 1]; in litex_clk_lookup_lock()
234 int assert = (1 << (drp[reg].size * BITS_PER_BYTE)) - 1; in litex_clk_assert_reg()
251 timeout = ldev->timeout.lock; in litex_clk_wait()
253 timeout = ldev->timeout.drdy; in litex_clk_wait()
257 timeout--; in litex_clk_wait()
262 return -ETIME; in litex_clk_wait()
303 ldev->g_config.mul = 1; in litex_clk_update_global_config()
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/Zephyr-latest/subsys/bluetooth/controller/ll_sw/openisa/hal/RV32M1/
Dticker.h2 * Copyright (c) 2016-2018 Nordic Semiconductor ASA
5 * SPDX-License-Identifier: Apache-2.0
27 * one or two prescaler clock cycles due to synchronization logic.
57 /* Macro returning remainder in picoseconds (to fit in 32-bits) */
62 - ((uint64_t)HAL_TICKER_US_TO_TICKS(x) * \
74 /* Macro defining the margin for positioning re-scheduled nodes */
/Zephyr-latest/doc/services/pm/images/
Dcentral_method.svg1 <?xml version="1.0" encoding="UTF-8"?>
2 <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
3 …-color: rgb(255, 255, 255);" xmlns:xlink="http://www.w3.org/1999/xlink" version="1.1" width="841px…
/Zephyr-latest/samples/drivers/clock_control_litex/
DREADME.rst1 .. zephyr:code-sample:: clock-control-litex
2 :name: LiteX clock control driver
3 :relevant-api: clock_control_interface
5 Use LiteX clock control driver to generate multiple clock signals.
10 This sample is providing an overview of LiteX clock control driver capabilities.
11 The driver uses Mixed Mode Clock Manager (MMCM) module to generate up to 7 clocks with defined phas…
15 * LiteX-capable FPGA platform with MMCM modules (for example Digilent Arty A7 development board)
16 * SoC configuration with VexRiscv soft CPU and Xilinx 7-series MMCM interface in LiteX (S7MMCM modu…
17 * Optional: clock output signals redirected to output pins for testing
21 …guration of the driver, including default settings for clock outputs, is held in Device Tree clock…
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/Zephyr-latest/drivers/timer/
Dsmartbond_timer.c4 * SPDX-License-Identifier: Apache-2.0
21 #define MAX_TICKS (((COUNTER_SPAN / 2) - CYC_PER_TICK) / (CYC_PER_TICK))
23 /* Margin values are based on DA1469x characterization data */
49 TIMER2->TIMER2_RELOAD_REG = val & TIMER2_TIMER2_RELOAD_REG_TIM_RELOAD_Msk; in set_reload()
57 timer_val_reg = TIMER2->TIMER2_TIMER_VAL_REG & in timer_val_32()
74 timer_val_reg = TIMER2->TIMER2_TIMER_VAL_REG & in timer_val_32_noupdate()
109 if (CRG_TOP->CLK_RCX_REG & CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Msk) { in sys_clock_set_timeout()
111 * When LP clock is RCX, the watchdog is clocked by RCX clock in sys_clock_set_timeout()
114 watchdog_expire_ticks = SYS_WDOG->WATCHDOG_REG * 320; in sys_clock_set_timeout()
117 * When LP clock is not RCX, the watchdog is clocked by RC32K in sys_clock_set_timeout()
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/Zephyr-latest/boards/nxp/frdm_mcxn236/
Dboard.c3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
23 /* Core clock frequency: 150MHz */
25 /* System clock frequency. */
30 SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK; in enable_lpcac()
31 SYSCON->LPCAC_CTRL &= ~(SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK | in enable_lpcac()
52 /* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */ in power_mode_od()
66 /* Enable SCG clock */ in frdm_mcxn236_init()
69 /* FRO OSC setup - begin, enable the FRO for safety switching */ in frdm_mcxn236_init()
71 /* Switch to FRO 12M first to ensure we can change the clock setting */ in frdm_mcxn236_init()
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/Zephyr-latest/tests/posix/common/src/
Dclock.c5 * SPDX-License-Identifier: Apache-2.0
15 #define CLOCK_INVALID -1
19 /* Set a particular time. In this case, the output of: `date +%s -d 2018-01-01T15:45:01Z` */
33 return ts->tv_sec * NSEC_PER_SEC + ts->tv_nsec; in ts_to_ns()
38 ts->tv_sec = tv->tv_sec; in tv_to_ts()
39 ts->tv_nsec = tv->tv_usec * NSEC_PER_USEC; in tv_to_ts()
55 _decl_op(int64_t, tp_diff, -); /* a - b */
57 /* lo <= (a - b) < hi */
66 ZTEST(clock, test_clock_gettime) in ZTEST() argument
72 zassert_equal(clock_gettime(CLOCK_INVALID, &ts), -1); in ZTEST()
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/Zephyr-latest/tests/drivers/sdhc/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
28 io.clock = props.f_min; in sdhc_power_on()
84 io.clock = props.f_min; in ZTEST()
96 * by a large margin over the max. in ZTEST()
98 io.clock = props.f_max + SDHC_FREQUENCY_SLIP; in ZTEST()
/Zephyr-latest/samples/drivers/clock_control_litex/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
13 /* Select clock outputs for tests [0-6] */
62 /* LiteX Common Clock Driver tests */
138 * specific clock output depends on devicetree config in litex_clk_test_freq()
139 * (including margin) and also on other active clock in litex_clk_test_freq()
148 if (ret != 0 && ret != -ENOTSUP) { in litex_clk_test_freq()
159 i -= LITEX_TEST_FREQUENCY_STEP) { in litex_clk_test_freq()
164 if (ret != 0 && ret != -ENOTSUP) { in litex_clk_test_freq()
200 if (ret != 0 && ret != -ENOTSUP) { in litex_clk_test_phase()
239 if (ret != 0 && ret != -ENOTSUP) { in litex_clk_test_duty()
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/Zephyr-latest/boards/nxp/frdm_mcxn947/
Dboard.c3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
27 /* Core clock frequency: 150MHz */
29 /* System clock frequency. */
49 /* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */ in power_mode_od()
60 /* Make sure the FlexSPI clock is enabled before configuring the FlexSPI cache. */ in enable_cache64()
61 SYSCON->AHBCLKCTRLSET[0] |= SYSCON_AHBCLKCTRL0_FLEXSPI_MASK; in enable_cache64()
64 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK; in enable_cache64()
65 CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK; in enable_cache64()
67 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) { in enable_cache64()
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/Zephyr-latest/samples/subsys/usb/uac2_explicit_feedback/src/
Dfeedback_nrf53.c4 * SPDX-License-Identifier: Apache-2.0
34 * is enabled, because I2S LRCLK edges (and not the clock) are being counted by
41 * this sample uses target-specific code to perform the measurements. Note that
42 * the use of dedicated target-specific peripheral essentially eliminates
46 * Full-Speed isochronous feedback is Q10.10 unsigned integer left-justified in
47 * the 24-bits so it has Q10.14 format. This sample application puts zeroes to
109 LOG_ERR("nrfx timer init error (sample clk feedback) - Return value: %d", err); in feedback_edge_counter_setup()
142 LOG_ERR("nrfx timer init error (relative timer) - Return value: %d", err); in feedback_relative_timer_setup()
211 /* Convert timer clock (independent from both Audio clock and in update_sof_offset()
212 * USB host SOF clock) to fake sample clock shifted by P values. in update_sof_offset()
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/Zephyr-latest/dts/arm/st/f4/
Dstm32f4.dtsi7 * SPDX-License-Identifier: Apache-2.0
10 #include <arm/armv7-m.dtsi>
11 #include <zephyr/dt-bindings/adc/adc.h>
12 #include <zephyr/dt-bindings/clock/stm32f4_clock.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/gpio/gpio.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
16 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
17 #include <zephyr/dt-bindings/dma/stm32_dma.h>
18 #include <zephyr/dt-bindings/adc/stm32f4_adc.h>
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/Zephyr-latest/tests/kernel/sleep/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
20 #define TEST_THREAD_PRIORITY -4
21 #define HELPER_THREAD_PRIORITY -10
30 * unstable in terms of timing. The tick margin of at least 5 is necessary to
65 * 5. k_sleep() - no cancellation exists
91 * measurement. Qemu at least will leak the external world's clock
96 uint32_t dt = end - start; in sleep_time_valid()
120 end_tick - start_tick, ONE_SECOND_ALIGNED); in test_thread()
132 if (end_tick - start_tick > TICK_MARGIN) { in test_thread()
134 end_tick - start_tick); in test_thread()
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/Zephyr-latest/subsys/bluetooth/controller/
DKconfig.ll_sw_split3 # Copyright (c) 2016-2017 Nordic Semiconductor ASA
4 # SPDX-License-Identifier: Apache-2.0
120 # Hidden, Controller's Co-Operative high priority Rx thread stack size.
125 # Hidden, Controller's Co-Operative Rx thread stack size.
152 https://www.bluetooth.com/specifications/assigned-numbers/company-identifiers
168 Legacy Non-Directed Advertising mode.
180 zero-based numbering. When using with Zephyr host this option can be
233 module-str = "Bluetooth Controller ISO-AL"
237 bool "ISO-AL verbose debug logging"
241 Use this option to enable ISO-AL verbose debug logging.
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/Zephyr-latest/drivers/ethernet/
Deth_adin2111_priv.h4 * SPDX-License-Identifier: Apache-2.0
17 /* SPI frequency maximum, based on clock cycle time */
185 /* Number of buffer bytes in TxFIFO to provide frame margin upon writes */
193 /* Max setting to a max RCA of 255 68-bytes ckunks */
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/
Dull_sched.c2 * Copyright (c) 2018-2022 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
146 * Hence, use CONFIG_BT_CTLR_CENTRAL_SPACING without margin. in ull_sched_after_cen_slot_get()
149 * CONFIG_BT_CTLR_CENTRAL_SPACING, then add margin between in ull_sched_after_cen_slot_get()
169 return -ECHILD; in ull_sched_after_cen_slot_get()
175 struct lll_scan *lll = p->param; in ull_sched_mfy_after_cen_offset_get()
181 conn = HDR_LLL2ULL(lll->conn); in ull_sched_mfy_after_cen_offset_get()
183 ticks_slot_overhead = MAX(conn->ull.ticks_active_to_start, in ull_sched_mfy_after_cen_offset_get()
184 conn->ull.ticks_prepare_to_start); in ull_sched_mfy_after_cen_offset_get()
189 ticks_at_expire = p->ticks_at_expire; in ull_sched_mfy_after_cen_offset_get()
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