Lines Matching +full:clock +full:- +full:margin

3  * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
12 /* Core clock frequency: 150MHz */
15 /* System clock frequency. */
34 		FMU0->FCTRL =  in frdm_mcxa156_init()
35 			(FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));  in frdm_mcxa156_init()
36 		/* Specifies the operating voltage for the SRAM's read/write timing margin */  in frdm_mcxa156_init()
44 	CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */  in frdm_mcxa156_init()
51 		FMU0->FCTRL =  in frdm_mcxa156_init()
52 			(FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));  in frdm_mcxa156_init()
53 		/* Specifies the operating voltage for the SRAM's read/write timing margin */  in frdm_mcxa156_init()
63 	/*!< Set up clock selectors - Attach clocks to the peripheries */  in frdm_mcxa156_init()
188  * Clock Select Decides what input source the lptmr will clock from  in frdm_mcxa156_init()
190  * 0 <- Reserved  in frdm_mcxa156_init()
191  * 1 <- 16K FRO  in frdm_mcxa156_init()
192  * 2 <- Reserved  in frdm_mcxa156_init()
193  * 3 <- Combination of clocks configured in MRCC_LPTMR0_CLKSEL[MUX] field  in frdm_mcxa156_init()