2  * Copyright (c) 2022-2024 Vestas Wind Systems A/S
5  * SPDX-License-Identifier: Apache-2.0
20  * @brief Allowed sample point calculation margin in permille.
55 	/* CiA 601-2 recommended data phase bitrates */
78 	const uint32_t ts = 1 + timing->prop_seg + timing->phase_seg1 + timing->phase_seg2;  in assert_bitrate_correct()
83 	zassert_not_equal(timing->prescaler, 0, "prescaler is zero");  in assert_bitrate_correct()
86 	zassert_equal(err, 0, "failed to get core CAN clock");  in assert_bitrate_correct()
88 	bitrate_calc = core_clock / timing->prescaler / ts;  in assert_bitrate_correct()
105 	zassert_true(timing->sjw <= max->sjw, "sjw exceeds max");  in assert_timing_within_bounds()
106 	zassert_true(timing->prop_seg <= max->prop_seg, "prop_seg exceeds max");  in assert_timing_within_bounds()
107 	zassert_true(timing->phase_seg1 <= max->phase_seg1, "phase_seg1 exceeds max");  in assert_timing_within_bounds()
108 	zassert_true(timing->phase_seg2 <= max->phase_seg2, "phase_seg2 exceeds max");  in assert_timing_within_bounds()
109 	zassert_true(timing->prescaler <= max->prescaler, "prescaler exceeds max");  in assert_timing_within_bounds()
111 	zassert_true(timing->sjw >= min->sjw, "sjw lower than min");  in assert_timing_within_bounds()
112 	zassert_true(timing->prop_seg >= min->prop_seg, "prop_seg lower than min");  in assert_timing_within_bounds()
113 	zassert_true(timing->phase_seg1 >= min->phase_seg1, "phase_seg1 lower than min");  in assert_timing_within_bounds()
114 	zassert_true(timing->phase_seg2 >= min->phase_seg2, "phase_seg2 lower than min");  in assert_timing_within_bounds()
115 	zassert_true(timing->prescaler >= min->prescaler, "prescaler lower than min");  in assert_timing_within_bounds()
119  * @brief Assert that a sample point is within a specified margin
122  * within a given margin.
126  * @param sp_margin sample point margin in permille
130 	const uint32_t ts = 1 + timing->prop_seg + timing->phase_seg1 + timing->phase_seg2;  in assert_sp_within_margin()
131 	const uint16_t sp_calc = ((1 + timing->prop_seg + timing->phase_seg1) * 1000) / ts;  in assert_sp_within_margin()
134 		       "sample point %d not within calculated sample point %d +/- %d",  in assert_sp_within_margin()
154 	int sp_err = -EINVAL;  in test_timing_values()
158 	       test->bitrate, test->sp / 10, test->sp % 10);  in test_timing_values()
164 			sp_err = can_calc_timing_data(dev, &timing, test->bitrate, test->sp);  in test_timing_values()
171 		sp_err = can_calc_timing(dev, &timing, test->bitrate, test->sp);  in test_timing_values()
174 	if (sp_err == -ENOTSUP) {  in test_timing_values()
186 		assert_bitrate_correct(dev, &timing, test->bitrate);  in test_timing_values()
188 		assert_sp_within_margin(&timing, test->sp, SAMPLE_POINT_MARGIN);  in test_timing_values()
258 	zassert_equal(err, 0, "failed to get core CAN clock");  in can_timing_setup()
260 	printk("testing on device %s @ %u Hz\n", dev->name, core_clock);  in can_timing_setup()
277 				TC_PRINT("Warning: CiA 601-3 recommends a CAN FD core clock of "  in can_timing_setup()