3  * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
27 /* Core clock frequency: 150MHz */
29 /* System clock frequency. */
49 	/* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */  in power_mode_od()
60 	/* Make sure the FlexSPI clock is enabled before configuring the FlexSPI cache. */  in enable_cache64()
61 	SYSCON->AHBCLKCTRLSET[0] |= SYSCON_AHBCLKCTRL0_FLEXSPI_MASK;  in enable_cache64()
64 	CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK;  in enable_cache64()
65 	CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK;  in enable_cache64()
67 	while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) {  in enable_cache64()
70 	CACHE64_CTRL0->CCR = (CACHE64_CTRL_CCR_ENWRBUF_MASK | CACHE64_CTRL_CCR_ENCACHE_MASK);  in enable_cache64()
76 	CACHE64_POLSEL0->REG0_TOP = 0x7FFC00;  in enable_cache64()
77 	CACHE64_POLSEL0->REG1_TOP = 0x0;  in enable_cache64()
78 	CACHE64_POLSEL0->POLSEL =  in enable_cache64()
91 	/* Enable SCG clock */  in frdm_mcxn947_init()
94 	/* FRO OSC setup - begin, enable the FRO for safety switching */  in frdm_mcxn947_init()
96 	/* Switch to FRO 12M first to ensure we can change the clock setting */  in frdm_mcxn947_init()
99 	/* Configure Flash wait-states to support 1.2V voltage level and 150000000Hz frequency */  in frdm_mcxn947_init()
100 	FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U));  in frdm_mcxn947_init()
106 	/* Call function flexspi_clock_safe_config() to move FleXSPI clock to a stable  in frdm_mcxn947_init()
107 	 * clock source when updating the PLL if in XIP (execute code from FlexSPI memory  in frdm_mcxn947_init()
135 	/* Set up PLL1 for 80 MHz FlexCAN clock */  in frdm_mcxn947_init()
216 	SYSCON0->PRESETCTRL2 = SYSCON_PRESETCTRL2_ENET_RST_MASK;  in frdm_mcxn947_init()
217 	SYSCON0->PRESETCTRL2 &= ~SYSCON_PRESETCTRL2_ENET_RST_MASK;  in frdm_mcxn947_init()
219 	SYSCON->ENET_PHY_INTF_SEL = SYSCON_ENET_PHY_INTF_SEL_PHY_SEL(1);  in frdm_mcxn947_init()
262 	/* Setup the FlexSPI clock */  in frdm_mcxn947_init()
272 	/* Drive CLKOUT from main clock, divided by 25 to yield 6MHz clock  in frdm_mcxn947_init()
273 	 * The camera will use this clock signal to generate  in frdm_mcxn947_init()
292 	SPC0->ACTIVE_VDELAY = 0x0500;  in frdm_mcxn947_init()
296 	SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK;  in frdm_mcxn947_init()
297 	SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_DCDC_VDD_LVL(0x3) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(0x3) |  in frdm_mcxn947_init()
300 	while (SPC0->SC & SPC_SC_BUSY_MASK) {  in frdm_mcxn947_init()
302 	if (0u == (SCG0->LDOCSR & SCG_LDOCSR_LDOEN_MASK)) {  in frdm_mcxn947_init()
303 		SCG0->TRIM_LOCK = 0x5a5a0001U;  in frdm_mcxn947_init()
304 		SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK;  in frdm_mcxn947_init()
306 		while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK)) {  in frdm_mcxn947_init()
309 	SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK |  in frdm_mcxn947_init()
311 	SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK);  in frdm_mcxn947_init()
313 	SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT);  in frdm_mcxn947_init()
314 	SCG0->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK;  in frdm_mcxn947_init()
316 		if (SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) {  in frdm_mcxn947_init()
320 	SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK |  in frdm_mcxn947_init()
340  * Clock Select Decides what input source the lptmr will clock from  in frdm_mcxn947_init()
342  * 0 <- 12MHz FRO  in frdm_mcxn947_init()
343  * 1 <- 16K FRO  in frdm_mcxn947_init()
344  * 2 <- 32K OSC  in frdm_mcxn947_init()
345  * 3 <- Output from the OSC_SYS  in frdm_mcxn947_init()
367 	/* Enable 1MHz clock. */  in frdm_mcxn947_init()
368 	SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK;  in frdm_mcxn947_init()
374 	/* Attach PLL0 clock to I3C, 150MHz / 6 = 25MHz. */  in frdm_mcxn947_init()