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/Zephyr-latest/dts/bindings/video/
Dvideo-interfaces.yaml2 # SPDX-License-Identifier: Apache-2.0
16 scheme using '#address-cells', '#size-cells' and 'reg' properties is used.
19 specify #address-cells, #size-cells properties independently for the 'port' and
25 #address-cells = <1>;
26 #size-cells = <0>;
37 Two 'endpoint' nodes must be linked with each other via their 'remote-endpoint'
39 references are currently not possible. A 'remote-endpoint-label' string is used
40 instead to be able to specify, at least, the label of the peer remote-endpoint.
44 compatible = "zephyr,video-interfaces";
45 remote-endpoint-label = "sink";
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/Zephyr-latest/boards/nxp/imx95_evk/doc/
Dindex.rst6 The i.MX95 EVK (IMX95LPD5EVK-19) board is a platform designed to show the
8 It is an entry-level development board, which helps developers to get familiar
16 - i.MX 95 automotive applications processor
18 - The processor integrates up to six Arm Cortex-A55 cores, and supports
19 functional safety with built-in Arm Cortex-M33 and -M7 cores
21 - DRAM memory: 128-Gbit LPDDR5 DRAM
22 - eMMC: 64 GB Micron eMMC
23 - SPI NOR flash memory: 1 Gbit octal flash memory
24 - USB interface: Two USB ports: Type-A and Type-C
25 - Audio codec interface
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/Zephyr-latest/boards/nxp/ls1046ardb/doc/
Dindex.rst6 The LS1046A reference design board (RDB) is a high-performance computing,
10 of high-speed SerDes ports.
12 The Layerscape LS1046A processor integrates four 64-bit Arm(R) Cortex(R) A72
13 cores with packet processing acceleration and high-speed peripherals. The
25 - Four 32/64-bit Arm(R) Cortex(R)V8 A72 CPUs, up to 1.6 GHz core speed
26 - Supports 8 GB DDR4 SDRAM memory
27 - SDHC port connects directly to an adapter card slot, featuring 4 GB eMMCi
29 - One 512 MB SLC NAND flash with ECC support (1.8 V)
30 - CPLD connection: 8-bit registers in CPLD to configure mux/demux selections
31 - Support two 64 MB onboard QSPI NOR flash memories
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/Zephyr-latest/boards/renesas/rcar_spider_s4/doc/
Drcar_spider_a55.rst3 R-CAR Spider S4 (ARM64)
8 R-Car S4 enables to launch Car Server/CoGW with high performance, high-speed networking,
10 evolve into domains and zones. The R-Car S4 solution allows designers to re-use up to 88
11 percent of software code developed for 3rd generation R-Car SoCs and RH850 MCU applications.
12 The software package supports the real-time cores with various drivers and basic software
17 The R-Car S4 includes:
19 * eight 1.2GHz Arm Cortex-A55 cores, 2 cores x 4 clusters;
20 * 1.0 GHz Arm Cortex-R52 core (hardware Lock step is supported);
22 * memory controller for LPDDR4X-3200 with 32bit bus (16bit x 1ch + 16bit x 1ch) with ECC;
25 * PCI Express Gen4.0 interface (Dual lane x 2ch);
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/Zephyr-latest/drivers/video/
Dvideo_mcux_mipi_csi2rx.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/drivers/video-controls.h>
22 #define ABS(a, b) (a > b ? a - b : b - a)
51 const struct mipi_csi2rx_config *config = dev->config; in mipi_csi2rx_update_settings()
52 struct mipi_csi2rx_data *drv_data = dev->data; in mipi_csi2rx_update_settings()
59 ret = video_get_format(config->sensor_dev, ep, &fmt); in mipi_csi2rx_update_settings()
65 ret = video_get_ctrl(config->sensor_dev, VIDEO_CID_PIXEL_RATE, &sensor_pixel_rate); in mipi_csi2rx_update_settings()
73 return -ENOTSUP; in mipi_csi2rx_update_settings()
77 sensor_byte_clk = sensor_pixel_rate * bpp / drv_data->csi2rxConfig.laneNum / 8; in mipi_csi2rx_update_settings()
79 ret = clock_control_get_rate(drv_data->clock_dev, drv_data->clock_root, &root_clk_rate); in mipi_csi2rx_update_settings()
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/Zephyr-latest/boards/raspberrypi/rpi_5/doc/
Dindex.rst6 `Raspberry Pi 5 product-brief`_
11 - Broadcom BCM2712 2.4GHz quad-core 64-bit Arm Cortex-A76 CPU, with cryptography extensions, 512KB …
12 - VideoCore VII GPU, supporting OpenGL ES 3.1, Vulkan 1.2
13 - Dual 4Kp60 HDMI® display output with HDR support
14 - 4Kp60 HEVC decoder
15 - LPDDR4X-4267 SDRAM (4GB and 8GB SKUs available at launch)
16 - Dual-band 802.11ac Wi-Fi®
17 - Bluetooth 5.0 / Bluetooth Low Energy (BLE)
18 - microSD card slot, with support for high-speed SDR104 mode
19 - 2 x USB 3.0 ports, supporting simultaneous 5Gbps operation
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/Zephyr-latest/drivers/mipi_dsi/
Ddsi_mcux.c4 * SPDX-License-Identifier: Apache-2.0
20 /* Max output frequency of DPHY bit clock */
56 * bit clock for a given target frequency, such that the DPHY clock in dsi_mcux_best_clock()
59 * configure the DPHY to output the closest realizable clock frequency in dsi_mcux_best_clock()
114 cm = (vco_freq + (refclk_cn_freq - 1)) / refclk_cn_freq; in dsi_mcux_best_clock()
138 if ((cand_freq - target_freq) < best_diff) { in dsi_mcux_best_clock()
140 best_diff = (cand_freq - target_freq); in dsi_mcux_best_clock()
161 const struct display_mcux_mipi_dsi_config *config = dev->config; in dsi_mcux_attach()
169 dsi_config.numLanes = mdev->data_lanes; in dsi_mcux_attach()
170 dsi_config.autoInsertEoTp = config->auto_insert_eotp; in dsi_mcux_attach()
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Ddsi_mcux_2l.c4 * SPDX-License-Identifier: Apache-2.0
71 const struct mcux_mipi_dsi_config *config = dev->config; in dsi_mcux_dma_cb()
72 struct mcux_mipi_dsi_data *data = dev->data; in dsi_mcux_dma_cb()
79 DSI_DisableInterrupts(config->base, kDSI_InterruptGroup1ApbTxDone | in dsi_mcux_dma_cb()
81 DSI_GetAndClearInterruptStatus(config->base, &int_flags1, &int_flags2); in dsi_mcux_dma_cb()
82 k_sem_give(&data->transfer_sem); in dsi_mcux_dma_cb()
99 const struct mcux_mipi_dsi_config *config = dev->config; in dsi_mcux_tx_color()
100 struct mcux_mipi_dsi_data *data = dev->data; in dsi_mcux_tx_color()
105 return -ENOTSUP; /* DMA can only transfer on virtual channel 0 */ in dsi_mcux_tx_color()
109 data->smartdma_params.p_buffer = msg->tx_buf; in dsi_mcux_tx_color()
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Ddsi_stm32.c7 * SPDX-License-Identifier: Apache-2.0
61 const struct mipi_dsi_stm32_config *config = dev->config; in mipi_dsi_stm32_log_config()
62 struct mipi_dsi_stm32_data *data = dev->data; in mipi_dsi_stm32_log_config()
64 LOG_DBG("DISPLAY: pix %d kHz, lane %d kHz", data->pixel_clk_khz, data->lane_clk_khz); in mipi_dsi_stm32_log_config()
66 LOG_DBG(" AutomaticClockLaneControl 0x%x", data->hdsi.Init.AutomaticClockLaneControl); in mipi_dsi_stm32_log_config()
67 LOG_DBG(" TXEscapeCkdiv %u", data->hdsi.Init.TXEscapeCkdiv); in mipi_dsi_stm32_log_config()
68 LOG_DBG(" NumberOfLanes %u", data->hdsi.Init.NumberOfLanes); in mipi_dsi_stm32_log_config()
69 LOG_DBG(" PLLNDIV %u", data->pll_init.PLLNDIV); in mipi_dsi_stm32_log_config()
70 LOG_DBG(" PLLIDF %u", data->pll_init.PLLIDF); in mipi_dsi_stm32_log_config()
71 LOG_DBG(" PLLODF %u", data->pll_init.PLLODF); in mipi_dsi_stm32_log_config()
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/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dsoc.c2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
11 * This module provides routines to initialize and support board-level
39 /* Core clock frequency: 198000000Hz */
49 /* OSC clock */
59 /* OSC clock */
81 /* System clock frequency. */
152 /* enable usb ip clock */ in usb_device_clock_init()
154 /* save usb ip clock freq*/ in usb_device_clock_init()
157 /* enable usb ram clock */ in usb_device_clock_init()
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/Zephyr-latest/include/zephyr/drivers/i3c/
Dccc.h5 * SPDX-License-Identifier: Apache-2.0
117 /** Enter HDR Mode (HDR-DDR) (Broadcast) */
120 /** Enter HDR Mode 0 (HDR-DDR) (Broadcast) */
123 /** Enter HDR Mode 1 (HDR-TSP) (Broadcast) */
126 /** Enter HDR Mode 2 (HDR-TSL) (Broadcast) */
129 /** Enter HDR Mode 3 (HDR-BT) (Broadcast) */
171 /** Multi-Lane Data Transfer Control (Broadcast) */
243 * - For Write CCC, pointer to the byte array of data
244 * to be sent, which may contain the Sub-Command Byte
246 * - For Read CCC, pointer to the byte buffer for data
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/Zephyr-latest/boards/element14/warp7/doc/
Dindex.rst6 The i.MX7S SoC is a Hybrid multi-core processor composed of Single Cortex A7
19 - 6-axis Accelerometer Magnetometer: NXP FXOS8700CQ (I2C4 interface)
20 - 3-axis Gyroscope: NXP FXAS21002C (I2C4 interface)
21 - Altimeter: NXP MPL3115A2 (I2C4 interface)
22 - NXP NTAG NT3H1101 (I2C2 interface)
23 - Audio Codec: NXP SGTL5000 (I2C4 and SAI1 interfaces)
24 - S1 - Reset Button (POR_B signal)
25 - S2 - User Defined button (ENET1_RD1/GPIO7_IO1 signal)
26 - S3 - On/Off (MX7_ONOFF signal)
27 - Board to board connector (34 configurable pins)
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/Zephyr-latest/boards/technexion/pico_pi/doc/
Dindex.rst6 The i.MX7D SoC is a Hybrid multi-core processor composed of Single Cortex A7
14 The Pico-Pi Platform is composed of a CPU and IO board.
16 Pico-Pi IO Board
18 - S1 - On/Off (MX7_ONOFF signal)
19 - Board to board connector : Edison compatible connector (70 configurable pins)
20 - mikroBUS expansion connector ADC, GPIO, I²C, PWM, SPI, UART)
21 - 10-pin needle JTAG Connector
22 - Debug USB exposing One UART
23 - MIPI DSI 1 lane Connector
24 - LCD Touch Connector
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/Zephyr-latest/include/zephyr/drivers/
Di3c.h5 * SPDX-License-Identifier: Apache-2.0
42 * - BCR[7:6]: Device Role
43 * - 0: I3C Target
44 * - 1: I3C Controller capable
45 * - 2: Reserved
46 * - 3: Reserved
48 * - BCR[5]: Advanced Capabilities
49 * - 0: Does not support optional advanced capabilities.
50 * - 1: Supports optional advanced capabilities which
53 * - BCR[4]: Virtual Target Support
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