2  * Copyright 2022-2023, NXP
4  * SPDX-License-Identifier: Apache-2.0
11  * This module provides routines to initialize and support board-level
39 /* Core clock frequency: 198000000Hz */
49 	/* OSC clock */
59 	/* OSC clock */
81 /* System clock frequency. */
152 	/* enable usb ip clock */  in usb_device_clock_init()
154 	/* save usb ip clock freq*/  in usb_device_clock_init()
157 	/* enable usb ram clock */  in usb_device_clock_init()
159 	/* enable USB PHY PLL clock, the phy bus clock (480MHz) source is same with USB IP */  in usb_device_clock_init()
172 	 * some microseconds to make sure utmi clock valid  in usb_device_clock_init()
174 	/* enable usb1 host clock */  in usb_device_clock_init()
176 	/*  Wait until host_needclk de-asserts */  in usb_device_clock_init()
177 	while (SYSCTL0->USB0CLKSTAT & SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK) {  in usb_device_clock_init()
183 	USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;  in usb_device_clock_init()
184 	/* disable usb1 host clock */  in usb_device_clock_init()
203 	MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;  in soc_reset_hook()
211 /* Weak so that board can override with their own clock init routine. */
220 	/* Configure FRO clock source */  in rt5xx_clock_init()
223 	/* FRO_DIV1 is always enabled and used as Main clock during PLL update. */  in rt5xx_clock_init()
229 	 * Call function flexspi_clock_safe_config() to move FlexSPI clock to a stable  in rt5xx_clock_init()
230 	 * clock source to avoid instruction/data fetch issue when updating PLL and Main  in rt5xx_clock_init()
231 	 * clock if XIP(execute code on FLEXSPI memory).  in rt5xx_clock_init()
240 	/* Configure SYSOSC clock source. */  in rt5xx_clock_init()
250 	/* Configure SysPLL0 clock source. */  in rt5xx_clock_init()
252 	/* Enable MAIN PLL clock */  in rt5xx_clock_init()
254 	/* Enable AUX0 PLL clock */  in rt5xx_clock_init()
257 	/* Configure Audio PLL clock source. */  in rt5xx_clock_init()
259 	/* Enable Audio PLL clock */  in rt5xx_clock_init()
265 	/* Setup FRG0 clock */  in rt5xx_clock_init()
267 	/* Setup FRG12 clock */  in rt5xx_clock_init()
270 	/* Set up clock selectors - Attach clocks to the peripheries. */  in rt5xx_clock_init()
288 	/* attach AUDIO PLL clock to FLEXCOMM1 (I2S_PDM) */  in rt5xx_clock_init()
293 	/* attach AUDIO PLL clock to FLEXCOMM1 (I2S1) */  in rt5xx_clock_init()
297 	/* attach AUDIO PLL clock to FLEXCOMM3 (I2S3) */  in rt5xx_clock_init()
306 	/* Attach main clock to I3C */  in rt5xx_clock_init()
333 	/* Note- pixel clock follows formula  in rt5xx_clock_init()
335 	 * this means the clock divider will vary depending on  in rt5xx_clock_init()
338 	 * The root clock used here is the AUX0 PLL (PLL0 PFD2).  in rt5xx_clock_init()
352 	/* Enable write-through for FlexSPI1 space */  in rt5xx_clock_init()
353 	CACHE64_POLSEL0->REG1_TOP = 0x27FFFC00U;  in rt5xx_clock_init()
354 	CACHE64_POLSEL0->POLSEL = 0x11U;  in rt5xx_clock_init()
368 	/* usdhc depend on 32K clock also */  in rt5xx_clock_init()
404 	 * Call function flexspi_setup_clock() to set user configured clock source/divider  in rt5xx_clock_init()
415 	/* Setup clock frequency for FlexSPI1 */  in rt5xx_clock_init()
423 	SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_PD_MASK;  in rt5xx_clock_init()
424 	SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_LP_MASK;  in rt5xx_clock_init()
431 	/* Using the Audio PLL as input clock leads to better clock dividers  in rt5xx_clock_init()
435 	 * Select Audio PLL as clock source. This should produce a bit clock  in rt5xx_clock_init()
446 	/* Set main clock to FRO as deep sleep clock by default. */  in rt5xx_clock_init()
450 	/* attach AUDIO PLL clock to MCLK */  in rt5xx_clock_init()
453 	SYSCTL1->MCLKPINDIR = SYSCTL1_MCLKPINDIR_MCLKPINDIR_MASK;  in rt5xx_clock_init()
476 	 * The DPHY bit clock must be fast enough to send out the pixels,  in imxrt_pre_init_display_interface()
479 	 *     (Pixel clock * bit per output pixel) / number of MIPI data lane  in imxrt_pre_init_display_interface()
481 	 * DPHY supports up to 895.1MHz bit clock.  in imxrt_pre_init_display_interface()
487 	/* Note: AUX1 PLL clock is system pll clock * 18 / pfd.  in imxrt_pre_init_display_interface()
488 	 * system pll clock is configured at 528MHz by default.  in imxrt_pre_init_display_interface()
515 	/* Remove clock from DPHY */  in imxrt_deinit_display_interface()
539 	/* Some ROM versions may have errata leaving these pins in a non-reset state,  in soc_early_init_hook()
543 	IOPCTL->PIO[1][15] = 0;  in soc_early_init_hook()
544 	IOPCTL->PIO[3][28] = 0;  in soc_early_init_hook()
545 	IOPCTL->PIO[3][29] = 0;  in soc_early_init_hook()