1.. zephyr:board:: imx95_evk
2
3Overview
4********
5
6The i.MX95 EVK (IMX95LPD5EVK-19) board is a platform designed to show the
7most commonly used features of the i.MX 95 automotive applications processor.
8It is an entry-level development board, which helps developers to get familiar
9with the processor before investing a large amount of resources in more
10specific designs. The i.MX95 device on the board comes in a compact
1119 x 19 mm package.
12
13Hardware
14********
15
16- i.MX 95 automotive applications processor
17
18  - The processor integrates up to six Arm Cortex-A55 cores, and supports
19    functional safety with built-in Arm Cortex-M33 and -M7 cores
20
21- DRAM memory: 128-Gbit LPDDR5 DRAM
22- eMMC: 64 GB Micron eMMC
23- SPI NOR flash memory: 1 Gbit octal flash memory
24- USB interface: Two USB ports: Type-A and Type-C
25- Audio codec interface
26
27  - One audio codec WM8962BECSN/R with one TX and RX lane
28  - One 3.5 mm 4-pole CTIA standard audio jack
29  - One 4-pin connector to connect speaker
30
31- Ethernet interface
32
33  - ENET2 controller
34
35    - Connects to a 60-pin Ethernet connector
36    - Supports Ethernet PHY daughter cards that can be configured to operate
37      at 100 Mbit/s or 1000 Mbit/s
38
39  - ENET1 controller
40
41    - Supports 100 Mbit/s or 1000 Mbit/s RGMII Ethernet with one RJ45
42      connector connected with an external PHY, RTL8211
43
44  - 10 Gbit Ethernet controller
45
46    - Supports XFI and USXGMII interfaces with one 10 Gbit RJ45 ICM connected
47      with an external PHY, Marvell AQR113C
48
49- M.2 interface: One Wi-Fi/Bluetooth Murata Type-2EL module based on NXP AW693
50  chip supporting 2x2 Wi-Fi 6 and Bluetooth 5.2
51
52- MIPI CSI interface: Connects to one 36-pin miniSAS connector using x4 lane
53  configuration
54- MIPI CSIDSI interface: Connects to one 36-pin miniSAS connector using x4 lane
55  configuration
56- LVDS interface: two mini-SAS connectors each with x4-lane configuration
57- CAN interface: Two 4-pin CAN headers for external connection
58- SD card interface: one 4-bit SD3.0 microSD card
59- I2C interface: I2C1 to I2C7 controllers
60- FT4232H I2C interface: PCT2075 temperature sensor and current monitoring devices
61- DMIC interface: two digital microphones (DMIC) providing a single-bit PDM output
62- ADC interface: two 4-channel ADC header
63- Audio board interface
64
65  - Supports PCIe x4 slot for Quantum board connection
66  - Supports PCIe x8 slot for Audio I/O board connection
67
68- Debug interface
69
70  - One USB-to-UART/MPSSE device, FT4232H
71  - One USB 2.0 Type-C connector (J31) for FT4232H provides quad serial ports
72
73Supported Features
74==================
75
76The Zephyr ``imx95_evk/mimx9596/m7`` board target supports the following hardware features:
77
78+-----------+------------+-------------------------------------+
79| Interface | Controller | Driver/Component                    |
80+===========+============+=====================================+
81| NVIC      | on-chip    | interrupt controller                |
82+-----------+------------+-------------------------------------+
83| SYSTICK   | on-chip    | systick                             |
84+-----------+------------+-------------------------------------+
85| CLOCK     | on-chip    | clock_control                       |
86+-----------+------------+-------------------------------------+
87| PINMUX    | on-chip    | pinmux                              |
88+-----------+------------+-------------------------------------+
89| UART      | on-chip    | serial port                         |
90+-----------+------------+-------------------------------------+
91| I2C       | on-chip    | i2c                                 |
92+-----------+------------+-------------------------------------+
93| TPM       | on-chip    | tpm                                 |
94+-----------+------------+-------------------------------------+
95
96The Zephyr ``imx95_evk/mimx9596/a55`` and ``imx95_evk/mimx9596/a55/smp`` board targets support
97the following hardware features:
98
99+-----------+------------+-------------------------------------+
100| Interface | Controller | Driver/Component                    |
101+===========+============+=====================================+
102| GIC-v4    | on-chip    | interrupt controller                |
103+-----------+------------+-------------------------------------+
104| ARM TIMER | on-chip    | system clock                        |
105+-----------+------------+-------------------------------------+
106| CLOCK     | on-chip    | clock_control                       |
107+-----------+------------+-------------------------------------+
108| PINMUX    | on-chip    | pinmux                              |
109+-----------+------------+-------------------------------------+
110| UART      | on-chip    | serial port                         |
111+-----------+------------+-------------------------------------+
112
113System Clock
114------------
115
116This board configuration uses a system clock frequency of 24 MHz for Cortex-A55.
117Cortex-A55 Core runs up to 1.8 GHz.
118Cortex-M7 Core runs up to 800MHz in which SYSTICK runs on same frequency.
119
120Serial Port
121-----------
122
123This board configuration uses a single serial communication channel with the
124CPU's UART1 for Cortex-A55, UART3 for Cortex-M7.
125
126TPM
127---
128
129Two channels are enabled on TPM2 for PWM for M7. Signals can be observerd with
130oscilloscope.
131Channel 2 signal routed to resistance R881.
132Channel 3 signal routed to resistance R882.
133
134
135Programming and Debugging (A55)
136*******************************
137
138Use this configuration to run basic Zephyr applications and kernel tests,
139for example, with the :zephyr:code-sample:`synchronization` sample:
140
1411. Build and run the Non-SMP application
142
143.. zephyr-app-commands::
144   :zephyr-app: samples/synchronization
145   :host-os: unix
146   :board: imx95_evk/mimx9596/a55
147   :goals: build
148
149This will build an image (zephyr.bin) with the synchronization sample app.
150
151Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and
152plug the SD card into the board. Power it up and stop the u-boot execution at
153prompt.
154
155Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core1:
156
157.. code-block:: console
158
159    fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; cpu 1 release 0xd0000000
160
161
162Or use the following command to kick zephyr.bin to Cortex-A55 Core0:
163
164.. code-block:: console
165
166    fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; go 0xd0000000
167
168
169It will display the following console output:
170
171.. code-block:: console
172
173    *** Booting Zephyr OS build v3.6.0-4569-g483c01ca11a7 ***
174    thread_a: Hello World from cpu 0 on imx95_evk!
175    thread_b: Hello World from cpu 0 on imx95_evk!
176    thread_a: Hello World from cpu 0 on imx95_evk!
177    thread_b: Hello World from cpu 0 on imx95_evk!
178    thread_a: Hello World from cpu 0 on imx95_evk!
179
1802. Build and run the SMP application
181
182.. zephyr-app-commands::
183   :zephyr-app: samples/synchronization
184   :host-os: unix
185   :board: imx95_evk/mimx9596/a55/smp
186   :goals: build
187
188This will build an image (zephyr.bin) with the synchronization sample app.
189
190Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and
191plug the SD card into the board. Power it up and stop the u-boot execution at
192prompt.
193
194Use the following command to kick zephyr.bin to Cortex-A55 Core0:
195
196.. code-block:: console
197
198    fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; go 0xd0000000
199
200
201It will display the following console output:
202.. code-block:: console
203
204    *** Booting Zephyr OS build v3.7.0-rc3-15-g2f0beaea144a ***
205    Secondary CPU core 1 (MPID:0x100) is up
206    Secondary CPU core 2 (MPID:0x200) is up
207    Secondary CPU core 3 (MPID:0x300) is up
208    Secondary CPU core 4 (MPID:0x400) is up
209    Secondary CPU core 5 (MPID:0x500) is up
210    thread_a: Hello World from cpu 0 on imx95_evk!
211    thread_b: Hello World from cpu 4 on imx95_evk!
212    thread_a: Hello World from cpu 0 on imx95_evk!
213    thread_b: Hello World from cpu 3 on imx95_evk!
214    thread_a: Hello World from cpu 0 on imx95_evk!
215    thread_b: Hello World from cpu 1 on imx95_evk!
216    thread_a: Hello World from cpu 0 on imx95_evk!
217    thread_b: Hello World from cpu 5 on imx95_evk!
218    thread_a: Hello World from cpu 0 on imx95_evk!
219    thread_b: Hello World from cpu 2 on imx95_evk!
220
221Programming and Debugging (M7)
222******************************
223
224The i.MX System Manager (SM) is used on i.MX95, which is an application that runs on
225Cortex-M33 processor. The Cortex-M33 is the boot core, runs the boot ROM which loads
226the SM (and other boot code), and then branches to the SM. The SM then configures some
227aspects of the hardware such as isolation mechanisms and then starts other cores in the
228system. After starting these cores, it enters a service mode where it provides access
229to clocking, power, sensor, and pin control via a client RPC API based on ARM's
230`System Control and Management Interface (SCMI)`_.
231
232To program M7, an i.MX container image ``flash.bin`` must be made, which contains
233multiple elements required, like ELE+V2X firmware, System Manager, TCM OEI, Cortex-M7
234image and so on.
235
236The steps making flash.bin and programming should refer to ``Getting Started with
237MCUXpresso SDK for IMX95LPD5EVK-19.pdf`` in i.MX95 `MCUX SDK release`_. Note that
238for the DDR variant, one should use the Makefile targets containing the ``ddr`` keyword.
239
240See ``4.2 Run an example application``, just rename ``zephyr.bin`` to ``m7_image.bin``
241to make flash.bin and program to SD/eMMC.
242
243Zephyr supports two M7-based i.MX95 boards: ``imx95_evk/mimx9596/m7`` and
244``imx95_evk/mimx9596/m7/ddr``. The main difference between them is the memory
245used. ``imx95_evk/mimx9596/m7`` uses TCM (ITCM for code and, generally, read-only
246data and DTCM for R/W data), while ``imx95_evk/mimx9596/m7/ddr`` uses DDR.
247
2481. Building the :zephyr:code-sample:`hello_world` application for the TCM-based board
249
250.. zephyr-app-commands::
251   :zephyr-app: samples/hello_world
252   :board: imx95_evk/mimx9596/m7
253   :goals: build
254
2552. Building the :zephyr:code-sample:`hello_world` application for the DDR-based board
256
257.. zephyr-app-commands::
258   :zephyr-app: samples/hello_world
259   :board: imx95_evk/mimx9596/m7/ddr
260   :goals: build
261
262After making flash.bin and program to SD/eMMC, open a serial terminal, and reset the
263board. For the ``imx95_evk/mimx9596/m7`` board you should see something like:
264
265.. code-block:: console
266
267   *** Booting Zephyr OS build v3.6.0-4569-g483c01ca11a7 ***
268   Hello World! imx95_evk/mimx9596/m7
269
270while, for the ``imx95_evk/mimx9596/m7/ddr`` board, you should get the following output:
271
272.. code-block:: console
273
274   *** Booting Zephyr OS build v3.6.0-4569-g483c01ca11a7 ***
275   Hello World! imx95_evk/mimx9596/m7/ddr
276
277.. _System Control and Management Interface (SCMI):
278   https://developer.arm.com/documentation/den0056/latest/
279
280.. _i.MX Linux BSP release:
281   https://www.nxp.com/design/design-center/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applications-processors:IMXLINUX
282
283.. _MCUX SDK release:
284   https://mcuxpresso.nxp.com/
285
286References
287==========
288
289More information can refer to NXP official website:
290`NXP website`_.
291
292.. _NXP website:
293   https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors/i-mx-95-applications-processor-family-high-performance-safety-enabled-platform-with-eiq-neutron-npu:iMX95
294