Home
last modified time | relevance | path

Searched full:cfg (Results 1 – 25 of 1496) sorted by relevance

12345678910>>...60

/Zephyr-latest/drivers/dma/
Ddma_intel_adsp_hda.c34 const struct intel_adsp_hda_dma_cfg *const cfg = dev->config; in intel_adsp_hda_dma_host_in_config() local
39 __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); in intel_adsp_hda_dma_host_in_config()
43 __ASSERT(dma_cfg->channel_direction == cfg->direction, in intel_adsp_hda_dma_host_in_config()
49 res = intel_adsp_hda_set_buffer(cfg->base, cfg->regblock_size, channel, buf, in intel_adsp_hda_dma_host_in_config()
53 *DGMBS(cfg->base, cfg->regblock_size, channel) = in intel_adsp_hda_dma_host_in_config()
56 intel_adsp_hda_set_sample_container_size(cfg->base, cfg->regblock_size, channel, in intel_adsp_hda_dma_host_in_config()
68 const struct intel_adsp_hda_dma_cfg *const cfg = dev->config; in intel_adsp_hda_dma_host_out_config() local
73 __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); in intel_adsp_hda_dma_host_out_config()
77 __ASSERT(dma_cfg->channel_direction == cfg->direction, in intel_adsp_hda_dma_host_out_config()
84 res = intel_adsp_hda_set_buffer(cfg->base, cfg->regblock_size, channel, buf, in intel_adsp_hda_dma_host_out_config()
[all …]
/Zephyr-latest/subsys/modbus/
Dmodbus_serial.c34 struct modbus_serial_config *cfg = ctx->cfg; in modbus_serial_tx_on() local
36 if (cfg->de != NULL) { in modbus_serial_tx_on()
37 gpio_pin_set(cfg->de->port, cfg->de->pin, 1); in modbus_serial_tx_on()
40 uart_irq_tx_enable(cfg->dev); in modbus_serial_tx_on()
45 struct modbus_serial_config *cfg = ctx->cfg; in modbus_serial_tx_off() local
47 uart_irq_tx_disable(cfg->dev); in modbus_serial_tx_off()
48 if (cfg->de != NULL) { in modbus_serial_tx_off()
49 gpio_pin_set(cfg->de->port, cfg->de->pin, 0); in modbus_serial_tx_off()
55 struct modbus_serial_config *cfg = ctx->cfg; in modbus_serial_rx_on() local
57 if (cfg->re != NULL) { in modbus_serial_rx_on()
[all …]
/Zephyr-latest/drivers/modem/
Dmodem_socket.c22 uint16_t modem_socket_next_packet_size(struct modem_socket_config *cfg, struct modem_socket *sock) in modem_socket_next_packet_size() argument
26 k_sem_take(&cfg->sem_lock, K_FOREVER); in modem_socket_next_packet_size()
35 k_sem_give(&cfg->sem_lock); in modem_socket_next_packet_size()
72 int modem_socket_packet_size_update(struct modem_socket_config *cfg, struct modem_socket *sock, in modem_socket_packet_size_update() argument
81 k_sem_take(&cfg->sem_lock, K_FOREVER); in modem_socket_packet_size_update()
92 k_sem_give(&cfg->sem_lock); in modem_socket_packet_size_update()
120 k_sem_give(&cfg->sem_lock); in modem_socket_packet_size_update()
128 k_sem_give(&cfg->sem_lock); in modem_socket_packet_size_update()
138 k_sem_give(&cfg->sem_lock); in modem_socket_packet_size_update()
150 int modem_socket_get(struct modem_socket_config *cfg, int family, int type, int proto) in modem_socket_get() argument
[all …]
/Zephyr-latest/drivers/serial/
Duart_lpc11u6x.c19 const struct lpc11u6x_uart0_config *cfg = dev->config; in lpc11u6x_uart0_poll_in() local
21 if (!(cfg->uart0->lsr & LPC11U6X_UART0_LSR_RDR)) { in lpc11u6x_uart0_poll_in()
24 *c = cfg->uart0->rbr; in lpc11u6x_uart0_poll_in()
31 const struct lpc11u6x_uart0_config *cfg = dev->config; in lpc11u6x_uart0_poll_out() local
33 while (!(cfg->uart0->lsr & LPC11U6X_UART0_LSR_THRE)) { in lpc11u6x_uart0_poll_out()
35 cfg->uart0->thr = c; in lpc11u6x_uart0_poll_out()
40 const struct lpc11u6x_uart0_config *cfg = dev->config; in lpc11u6x_uart0_err_check() local
44 lsr = cfg->uart0->lsr; in lpc11u6x_uart0_err_check()
78 const struct lpc11u6x_uart0_config *cfg, in lpc11u6x_uart0_config_baudrate() argument
89 clock_control_get_rate(clk_drv, (clock_control_subsys_t) cfg->clkid, in lpc11u6x_uart0_config_baudrate()
[all …]
Dusart_gd32.c56 const struct gd32_usart_config *const cfg = dev->config; in usart_gd32_init() local
62 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in usart_gd32_init()
71 switch (cfg->parity) { in usart_gd32_init()
89 (clock_control_subsys_t)&cfg->clkid); in usart_gd32_init()
91 (void)reset_line_toggle_dt(&cfg->reset); in usart_gd32_init()
93 usart_baudrate_set(cfg->reg, data->baud_rate); in usart_gd32_init()
94 usart_parity_config(cfg->reg, parity); in usart_gd32_init()
95 usart_word_length_set(cfg->reg, word_length); in usart_gd32_init()
97 usart_stop_bit_set(cfg->reg, USART_STB_1BIT); in usart_gd32_init()
98 usart_receive_config(cfg->reg, USART_RECEIVE_ENABLE); in usart_gd32_init()
[all …]
Duart_sam.c47 const struct uart_sam_dev_cfg *const cfg = dev->config; in uart_sam_poll_in() local
49 Uart * const uart = cfg->regs; in uart_sam_poll_in()
63 const struct uart_sam_dev_cfg *const cfg = dev->config; in uart_sam_poll_out() local
65 Uart * const uart = cfg->regs; in uart_sam_poll_out()
77 const struct uart_sam_dev_cfg *const cfg = dev->config; in uart_sam_err_check() local
79 volatile Uart * const uart = cfg->regs; in uart_sam_err_check()
103 const struct uart_sam_dev_cfg *const cfg = dev->config; in uart_sam_baudrate_set() local
105 volatile Uart * const uart = cfg->regs; in uart_sam_baudrate_set()
145 const struct uart_sam_dev_cfg *const cfg = dev->config; in uart_sam_get_parity() local
147 volatile Uart * const uart = cfg->regs; in uart_sam_get_parity()
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dnxp-s32-pinctrl.h36 #define NXP_S32_PINMUX_MSCR_SSS(cfg) \ argument
37 (((cfg) & NXP_S32_MSCR_SSS_MASK) << NXP_S32_MSCR_SSS_SHIFT)
39 #define NXP_S32_PINMUX_IMCR_SSS(cfg) \ argument
40 (((cfg) & NXP_S32_IMCR_SSS_MASK) << NXP_S32_IMCR_SSS_SHIFT)
42 #define NXP_S32_PINMUX_IMCR_IDX(cfg) \ argument
43 (((cfg) & NXP_S32_IMCR_IDX_MASK) << NXP_S32_IMCR_IDX_SHIFT)
45 #define NXP_S32_PINMUX_MSCR_IDX(cfg) \ argument
46 (((cfg) & NXP_S32_MSCR_IDX_MASK) << NXP_S32_MSCR_IDX_SHIFT)
48 #define NXP_S32_PINMUX_MSCR_SIUL2_IDX(cfg) \ argument
49 (((cfg) & NXP_S32_MSCR_SIUL2_IDX_MASK) << NXP_S32_MSCR_SIUL2_IDX_SHIFT)
[all …]
/Zephyr-latest/drivers/dai/nxp/esai/
Desai.c35 struct esai_transceiver_config *cfg) in esai_get_clock_rate_config() argument
40 if (!cfg) { in esai_get_clock_rate_config()
87 cfg->hclk_bypass = true; in esai_get_clock_rate_config()
97 cfg->hclk_prescaler_en = true; in esai_get_clock_rate_config()
113 cfg->hclk_div_ratio = hclk_div_ratio; in esai_get_clock_rate_config()
122 if (variable_hclk || cfg->hclk_bypass) { in esai_get_clock_rate_config()
131 cfg->hclk_prescaler_en = true; in esai_get_clock_rate_config()
137 cfg->bclk_div_ratio = 1; in esai_get_clock_rate_config()
138 cfg->hclk_div_ratio = hclk_div_ratio; in esai_get_clock_rate_config()
148 cfg->bclk_div_ratio = bclk_div_ratio; in esai_get_clock_rate_config()
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_control_sam_pmc.c26 const struct atmel_sam_pmc_config *cfg = (const struct atmel_sam_pmc_config *)sys; in atmel_sam_clock_control_on() local
28 if (cfg == NULL) { in atmel_sam_clock_control_on()
33 LOG_DBG("Type: %x, Id: %d", cfg->clock_type, cfg->peripheral_id); in atmel_sam_clock_control_on()
35 switch (cfg->clock_type) { in atmel_sam_clock_control_on()
37 soc_pmc_peripheral_enable(cfg->peripheral_id); in atmel_sam_clock_control_on()
52 const struct atmel_sam_pmc_config *cfg = (const struct atmel_sam_pmc_config *)sys; in atmel_sam_clock_control_off() local
54 if (cfg == NULL) { in atmel_sam_clock_control_off()
59 LOG_DBG("Type: %x, Id: %d", cfg->clock_type, cfg->peripheral_id); in atmel_sam_clock_control_off()
61 switch (cfg->clock_type) { in atmel_sam_clock_control_off()
63 soc_pmc_peripheral_disable(cfg->peripheral_id); in atmel_sam_clock_control_off()
[all …]
/Zephyr-latest/subsys/ipc/ipc_service/lib/
Dpbuf.c31 static int validate_cfg(const struct pbuf_cfg *cfg) in validate_cfg() argument
34 if (!cfg || !cfg->rd_idx_loc || !cfg->wr_idx_loc || !cfg->data_loc) { in validate_cfg()
39 if (!IS_PTR_ALIGNED_BYTES(cfg->rd_idx_loc, MAX(cfg->dcache_alignment, _PBUF_IDX_SIZE)) || in validate_cfg()
40 !IS_PTR_ALIGNED_BYTES(cfg->wr_idx_loc, MAX(cfg->dcache_alignment, _PBUF_IDX_SIZE)) || in validate_cfg()
41 !IS_PTR_ALIGNED_BYTES(cfg->data_loc, _PBUF_IDX_SIZE)) { in validate_cfg()
46 if (cfg->len < _PBUF_MIN_DATA_LEN || !IS_PTR_ALIGNED_BYTES(cfg->len, _PBUF_IDX_SIZE)) { in validate_cfg()
51 if (!(cfg->rd_idx_loc < cfg->wr_idx_loc) || in validate_cfg()
52 !((uint8_t *)cfg->wr_idx_loc < cfg->data_loc) || in validate_cfg()
53 !(((uint8_t *)cfg->rd_idx_loc + MAX(_PBUF_IDX_SIZE, cfg->dcache_alignment)) == in validate_cfg()
54 (uint8_t *)cfg->wr_idx_loc)) { in validate_cfg()
[all …]
/Zephyr-latest/drivers/w1/
Dw1_ds2477_85_common.c22 const struct w1_ds2477_85_config *cfg = dev->config; in ds2477_85_write_port_config() local
29 ret = i2c_write_dt(&cfg->i2c_spec, buf, (CMD_WR_W1_PORT_CFG_LEN + CMD_OVERHEAD_LEN)); in ds2477_85_write_port_config()
34 k_usleep(cfg->t_op_us); in ds2477_85_write_port_config()
36 ret = i2c_read_dt(&cfg->i2c_spec, buf, 2); in ds2477_85_write_port_config()
49 const struct w1_ds2477_85_config *cfg = dev->config; in ds2477_85_read_port_config() local
55 ret = i2c_write_dt(&cfg->i2c_spec, buf, (CMD_RD_W1_PORT_CFG_LEN + CMD_OVERHEAD_LEN)); in ds2477_85_read_port_config()
60 k_usleep(cfg->t_op_us); in ds2477_85_read_port_config()
62 ret = i2c_read_dt(&cfg->i2c_spec, buf, 4); in ds2477_85_read_port_config()
77 const struct w1_ds2477_85_config *cfg = dev->config; in ds2477_85_reset_master() local
81 ret = i2c_write_dt(&cfg->i2c_spec, buf, 1); in ds2477_85_reset_master()
[all …]
/Zephyr-latest/drivers/spi/
Dspi_mchp_mss.c117 static inline uint32_t mss_spi_read(const struct mss_spi_config *cfg, mm_reg_t offset) in mss_spi_read() argument
119 return sys_read32(cfg->base + offset); in mss_spi_read()
122 static inline void mss_spi_write(const struct mss_spi_config *cfg, mm_reg_t offset, uint32_t val) in mss_spi_write() argument
124 sys_write32(val, cfg->base + offset); in mss_spi_write()
127 static inline void mss_spi_hw_tfsz_set(const struct mss_spi_config *cfg, int len) in mss_spi_hw_tfsz_set() argument
131 mss_spi_write(cfg, MSS_SPI_REG_FRAMESUP, (len & MSS_SPI_FRAMESUP_UP_BYTES_MSK)); in mss_spi_hw_tfsz_set()
132 control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL); in mss_spi_hw_tfsz_set()
135 mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control); in mss_spi_hw_tfsz_set()
138 static inline void mss_spi_enable_controller(const struct mss_spi_config *cfg) in mss_spi_enable_controller() argument
142 control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL); in mss_spi_enable_controller()
[all …]
/Zephyr-latest/drivers/pwm/
Dpwm_gecko.c31 const struct pwm_gecko_config *cfg = dev->config; in pwm_gecko_set_cycles() local
33 if (BUS_RegMaskedRead(&cfg->timer->CC[channel].CTRL, in pwm_gecko_set_cycles()
37 BUS_RegMaskedWrite(&cfg->timer->ROUTE, in pwm_gecko_set_cycles()
39 cfg->location << _TIMER_ROUTE_LOCATION_SHIFT); in pwm_gecko_set_cycles()
40 BUS_RegMaskedSet(&cfg->timer->ROUTE, 1 << channel); in pwm_gecko_set_cycles()
42 BUS_RegMaskedWrite(&cfg->timer->ROUTELOC0, in pwm_gecko_set_cycles()
45 cfg->location << (channel * _TIMER_ROUTELOC0_CC1LOC_SHIFT)); in pwm_gecko_set_cycles()
46 BUS_RegMaskedSet(&cfg->timer->ROUTEPEN, 1 << channel); in pwm_gecko_set_cycles()
52 TIMER_InitCC(cfg->timer, channel, &compare_config); in pwm_gecko_set_cycles()
55 cfg->timer->CC[channel].CTRL |= (flags & PWM_POLARITY_INVERTED) ? in pwm_gecko_set_cycles()
[all …]
Dpwm_stm32.c316 const struct pwm_stm32_config *cfg = dev->config; in pwm_stm32_set_cycles() local
331 if (!IS_TIM_32B_COUNTER_INSTANCE(cfg->timer) && in pwm_stm32_set_cycles()
338 if (LL_TIM_IsEnabledIT_CC1(cfg->timer) || LL_TIM_IsEnabledIT_CC2(cfg->timer) || in pwm_stm32_set_cycles()
339 LL_TIM_IsEnabledIT_CC3(cfg->timer) || LL_TIM_IsEnabledIT_CC4(cfg->timer)) { in pwm_stm32_set_cycles()
368 LL_TIM_CC_DisableChannel(cfg->timer, current_ll_channel); in pwm_stm32_set_cycles()
372 if (cfg->countermode == LL_TIM_COUNTERMODE_UP) { in pwm_stm32_set_cycles()
375 } else if (cfg->countermode == LL_TIM_COUNTERMODE_DOWN) { in pwm_stm32_set_cycles()
380 } else if (is_center_aligned(cfg->countermode)) { in pwm_stm32_set_cycles()
387 if (!LL_TIM_CC_IsEnabledChannel(cfg->timer, current_ll_channel)) { in pwm_stm32_set_cycles()
401 oc_init.OCState = LL_TIM_CC_IsEnabledChannel(cfg->timer, ll_channel) in pwm_stm32_set_cycles()
[all …]
/Zephyr-latest/scripts/west_commands/runners/
Dhifive1.py15 def __init__(self, cfg): argument
16 super().__init__(cfg)
17 self.openocd_config = path.join(cfg.board_dir, 'support', 'openocd.cfg')
32 def do_create(cls, cfg, args): argument
33 if cfg.gdb is None:
36 return HiFive1BinaryRunner(cfg)
39 self.require(self.cfg.openocd)
40 self.require(self.cfg.gdb)
41 openocd_cmd = ([self.cfg.openocd, '-f', self.openocd_config])
42 gdb_cmd = ([self.cfg.gdb, self.cfg.elf_file, '--batch',
/Zephyr-latest/drivers/input/
Dinput_kbd_matrix.c31 const struct input_kbd_matrix_common_config *cfg = dev->config; in input_kbd_matrix_ghosting() local
32 const kbd_row_t *state = cfg->matrix_new_state; in input_kbd_matrix_ghosting()
48 for (int c = 0; c < cfg->col_size; c++) { in input_kbd_matrix_ghosting()
53 for (int c_next = c + 1; c_next < cfg->col_size; c_next++) { in input_kbd_matrix_ghosting()
76 const struct input_kbd_matrix_common_config *cfg = dev->config; in input_kbd_matrix_drive_column() local
77 const struct input_kbd_matrix_api *api = cfg->api; in input_kbd_matrix_drive_column()
99 const struct input_kbd_matrix_common_config *cfg = dev->config; in input_kbd_matrix_scan() local
100 const struct input_kbd_matrix_api *api = cfg->api; in input_kbd_matrix_scan()
104 for (int col = 0; col < cfg->col_size; col++) { in input_kbd_matrix_scan()
105 if (cfg->actual_key_mask != NULL && in input_kbd_matrix_scan()
[all …]
/Zephyr-latest/drivers/regulator/
Dregulator_gpio.c35 const struct regulator_gpio_config *cfg = dev->config; in regulator_gpio_apply_state() local
37 for (unsigned int gpio_idx = 0; gpio_idx < cfg->num_gpios; gpio_idx++) { in regulator_gpio_apply_state()
41 ret = gpio_pin_get_dt(&cfg->gpios[gpio_idx]); in regulator_gpio_apply_state()
48 ret = gpio_pin_set_dt(&cfg->gpios[gpio_idx], new_state_of_gpio); in regulator_gpio_apply_state()
61 const struct regulator_gpio_config *cfg = dev->config; in regulator_gpio_enable() local
64 if (cfg->enable.port == NULL) { in regulator_gpio_enable()
68 ret = gpio_pin_set_dt(&cfg->enable, 1); in regulator_gpio_enable()
79 const struct regulator_gpio_config *cfg = dev->config; in regulator_gpio_disable() local
81 if (cfg->enable.port == NULL) { in regulator_gpio_disable()
85 return gpio_pin_set_dt(&cfg->enable, 0); in regulator_gpio_disable()
[all …]
/Zephyr-latest/drivers/sensor/tdk/icm42605/
Dicm42605_setup.c19 const struct icm42605_config *cfg = dev->config; in icm42605_set_fs() local
23 result = inv_spi_read(&cfg->spi, REG_ACCEL_CONFIG0, &databuf, 1); in icm42605_set_fs()
31 result = inv_spi_single_write(&cfg->spi, REG_ACCEL_CONFIG0, &databuf); in icm42605_set_fs()
33 result = inv_spi_read(&cfg->spi, REG_GYRO_CONFIG0, &databuf, 1); in icm42605_set_fs()
42 result = inv_spi_single_write(&cfg->spi, REG_GYRO_CONFIG0, &databuf); in icm42605_set_fs()
53 const struct icm42605_config *cfg = dev->config; in icm42605_set_odr() local
63 result = inv_spi_read(&cfg->spi, REG_ACCEL_CONFIG0, &databuf, 1); in icm42605_set_odr()
99 result = inv_spi_single_write(&cfg->spi, REG_ACCEL_CONFIG0, &databuf); in icm42605_set_odr()
107 result = inv_spi_read(&cfg->spi, REG_GYRO_CONFIG0, &databuf, 1); in icm42605_set_odr()
139 result = inv_spi_single_write(&cfg->spi, REG_GYRO_CONFIG0, &databuf); in icm42605_set_odr()
[all …]
/Zephyr-latest/drivers/sensor/veaa_x_3/
Dveaa_x_3.c39 static uint16_t veaa_x_3_kpa_range(const struct veaa_x_3_cfg *cfg) in veaa_x_3_kpa_range() argument
41 return cfg->kpa_max - cfg->kpa_min; in veaa_x_3_kpa_range()
47 const struct veaa_x_3_cfg *cfg = dev->config; in veaa_x_3_attr_set() local
56 if (val->val1 > cfg->kpa_max || val->val1 < cfg->kpa_min) { in veaa_x_3_attr_set()
62 tmp = val->val1 - cfg->kpa_min; in veaa_x_3_attr_set()
63 if (u32_mul_overflow(tmp, BIT(cfg->dac_resolution) - 1, &tmp)) { in veaa_x_3_attr_set()
67 tmp /= veaa_x_3_kpa_range(cfg); in veaa_x_3_attr_set()
69 return dac_write_value(cfg->dac, cfg->dac_channel, tmp); in veaa_x_3_attr_set()
78 const struct veaa_x_3_cfg *cfg = dev->config; in veaa_x_3_attr_get() local
86 val->val1 = cfg->kpa_min; in veaa_x_3_attr_get()
[all …]
/Zephyr-latest/drivers/interrupt_controller/
Dintc_mtk_adsp.c19 const struct intc_mtk_cfg *cfg = dev->config; in intc_mtk_adsp_get_enable() local
21 return (*cfg->enable_reg | (BIT(irq) & cfg->irq_mask)) != 0; in intc_mtk_adsp_get_enable()
26 const struct intc_mtk_cfg *cfg = dev->config; in intc_mtk_adsp_set_enable() local
28 irq_enable(cfg->xtensa_irq); in intc_mtk_adsp_set_enable()
30 if ((BIT(irq) & cfg->irq_mask) != 0) { in intc_mtk_adsp_set_enable()
32 *cfg->enable_reg |= BIT(irq); in intc_mtk_adsp_set_enable()
34 *cfg->enable_reg &= ~BIT(irq); in intc_mtk_adsp_set_enable()
41 const struct intc_mtk_cfg *cfg = ((struct device *)arg)->config; in intc_isr() local
42 uint32_t irqs = *cfg->status_reg & cfg->irq_mask; in intc_isr()
46 uint32_t off = cfg->sw_isr_off + irq; in intc_isr()
[all …]
/Zephyr-latest/boards/silabs/dev_kits/sltb004a/
Dboard.c17 static int enable_supply(const struct supply_cfg *cfg) in enable_supply() argument
21 if (device_is_ready(cfg->gpio)) { in enable_supply()
22 gpio_pin_configure(cfg->gpio, cfg->pin, in enable_supply()
23 GPIO_OUTPUT | cfg->flags); in enable_supply()
24 gpio_pin_set(cfg->gpio, cfg->pin, 1); in enable_supply()
33 struct supply_cfg cfg; in efr32mg_sltb004a_init() local
36 (void)cfg; in efr32mg_sltb004a_init()
41 cfg = (struct supply_cfg){ in efr32mg_sltb004a_init()
48 rc = enable_supply(&cfg); in efr32mg_sltb004a_init()
/Zephyr-latest/subsys/net/ip/
Dipv4_autoconf.c60 struct net_if_config *cfg; in acd_event_handler() local
63 cfg = net_if_get_config(iface); in acd_event_handler()
64 if (!cfg) { in acd_event_handler()
68 if (cfg->ipv4auto.iface == NULL) { in acd_event_handler()
84 if (!net_ipv4_addr_cmp(&cfg->ipv4auto.requested_ip, addr)) { in acd_event_handler()
90 cfg->ipv4auto.state = NET_IPV4_AUTOCONF_ASSIGNED; in acd_event_handler()
97 cfg->ipv4auto.state = NET_IPV4_AUTOCONF_INIT; in acd_event_handler()
98 ipv4_autoconf_addr_set(&cfg->ipv4auto); in acd_event_handler()
108 struct net_if_config *cfg; in net_ipv4_autoconf_start() local
114 cfg = net_if_get_config(iface); in net_ipv4_autoconf_start()
[all …]
/Zephyr-latest/drivers/sensor/hc_sr04/
Dhc_sr04.c35 static int hcsr04_configure_gpios(const struct hcsr04_config *cfg) in hcsr04_configure_gpios() argument
39 if (!gpio_is_ready_dt(&cfg->trigger_gpios)) { in hcsr04_configure_gpios()
40 LOG_ERR("GPIO '%s' not ready", cfg->trigger_gpios.port->name); in hcsr04_configure_gpios()
43 ret = gpio_pin_configure_dt(&cfg->trigger_gpios, GPIO_OUTPUT_LOW); in hcsr04_configure_gpios()
45 LOG_ERR("Failed to configure '%s' as output: %d", cfg->trigger_gpios.port->name, in hcsr04_configure_gpios()
50 if (!gpio_is_ready_dt(&cfg->echo_gpios)) { in hcsr04_configure_gpios()
51 LOG_ERR("GPIO '%s' not ready", cfg->echo_gpios.port->name); in hcsr04_configure_gpios()
54 ret = gpio_pin_configure_dt(&cfg->echo_gpios, GPIO_INPUT); in hcsr04_configure_gpios()
56 LOG_ERR("Failed to configure '%s' as output: %d", cfg->echo_gpios.port->name, ret); in hcsr04_configure_gpios()
63 static int hcsr04_configure_interrupt(const struct hcsr04_config *cfg, struct hcsr04_data *data) in hcsr04_configure_interrupt() argument
[all …]
/Zephyr-latest/drivers/counter/
Dcounter_max32_timer.c44 const struct max32_tmr_config *cfg = dev->config; in api_start() local
46 Wrap_MXC_TMR_EnableInt(cfg->regs); in api_start()
47 MXC_TMR_Start(cfg->regs); in api_start()
54 const struct max32_tmr_config *cfg = dev->config; in api_stop() local
56 Wrap_MXC_TMR_DisableInt(cfg->regs); in api_stop()
57 MXC_TMR_Stop(cfg->regs); in api_stop()
64 const struct max32_tmr_config *cfg = dev->config; in api_get_value() local
66 *ticks = MXC_TMR_GetCount(cfg->regs); in api_get_value()
72 const struct max32_tmr_config *cfg = dev->config; in api_set_top_value() local
78 if (counter_cfg->ticks != cfg->info.max_top_value) { in api_set_top_value()
[all …]
/Zephyr-latest/drivers/i2c/
Di2c_gd32.c57 static inline void i2c_gd32_enable_interrupts(const struct i2c_gd32_config *cfg) in i2c_gd32_enable_interrupts() argument
59 I2C_CTL1(cfg->reg) |= I2C_CTL1_ERRIE; in i2c_gd32_enable_interrupts()
60 I2C_CTL1(cfg->reg) |= I2C_CTL1_EVIE; in i2c_gd32_enable_interrupts()
61 I2C_CTL1(cfg->reg) |= I2C_CTL1_BUFIE; in i2c_gd32_enable_interrupts()
64 static inline void i2c_gd32_disable_interrupts(const struct i2c_gd32_config *cfg) in i2c_gd32_disable_interrupts() argument
66 I2C_CTL1(cfg->reg) &= ~I2C_CTL1_ERRIE; in i2c_gd32_disable_interrupts()
67 I2C_CTL1(cfg->reg) &= ~I2C_CTL1_EVIE; in i2c_gd32_disable_interrupts()
68 I2C_CTL1(cfg->reg) &= ~I2C_CTL1_BUFIE; in i2c_gd32_disable_interrupts()
72 const struct i2c_gd32_config *cfg) in i2c_gd32_xfer_read() argument
75 *data->current->buf = I2C_DATA(cfg->reg); in i2c_gd32_xfer_read()
[all …]

12345678910>>...60