1 /*
2 * Copyright (c) 2022 Microchip Technology Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT microchip_mpfs_spi
8
9 #include <zephyr/device.h>
10 #include <zephyr/drivers/spi.h>
11 #include <zephyr/drivers/spi/rtio.h>
12 #include <zephyr/sys/sys_io.h>
13 #include <zephyr/sys/util.h>
14 #include <zephyr/logging/log.h>
15 #include <zephyr/irq.h>
16
17 LOG_MODULE_REGISTER(mss_spi, CONFIG_SPI_LOG_LEVEL);
18
19 #include "spi_context.h"
20
21 /* MSS SPI Register offsets */
22 #define MSS_SPI_REG_CONTROL (0x00)
23 #define MSS_SPI_REG_TXRXDF_SIZE (0x04)
24 #define MSS_SPI_REG_STATUS (0x08)
25 #define MSS_SPI_REG_INT_CLEAR (0x0c)
26 #define MSS_SPI_REG_RX_DATA (0x10)
27 #define MSS_SPI_REG_TX_DATA (0x14)
28 #define MSS_SPI_REG_CLK_GEN (0x18)
29 #define MSS_SPI_REG_SS (0x1c)
30 #define MSS_SPI_REG_MIS (0x20)
31 #define MSS_SPI_REG_RIS (0x24)
32 #define MSS_SPI_REG_CONTROL2 (0x28)
33 #define MSS_SPI_REG_COMMAND (0x2c)
34 #define MSS_SPI_REG_PKTSIZE (0x30)
35 #define MSS_SPI_REG_CMD_SIZE (0x34)
36 #define MSS_SPI_REG_HWSTATUS (0x38)
37 #define MSS_SPI_REG_FRAMESUP (0x50)
38
39 /* SPICR bit definitions */
40 #define MSS_SPI_CONTROL_ENABLE BIT(0)
41 #define MSS_SPI_CONTROL_MASTER BIT(1)
42 #define MSS_SPI_CONTROL_PROTO_MSK BIT(2)
43 #define MSS_SPI_CONTROL_PROTO_MOTO (0 << 2)
44 #define MSS_SPI_CONTROL_RX_DATA_INT BIT(4)
45 #define MSS_SPI_CONTROL_TX_DATA_INT BIT(5)
46 #define MSS_SPI_CONTROL_RX_OVER_INT BIT(6)
47 #define MSS_SPI_CONTROL_TX_UNDER_INT BIT(7)
48 #define MSS_SPI_CONTROL_CNT_MSK (0xffff << 8)
49 #define MSS_SPI_CONTROL_CNT_SHF (8)
50 #define MSS_SPI_CONTROL_SPO BIT(24)
51 #define MSS_SPI_CONTROL_SPH BIT(25)
52 #define MSS_SPI_CONTROL_SPS BIT(26)
53 #define MSS_SPI_CONTROL_FRAMEURUN BIT(27)
54 #define MSS_SPI_CONTROL_CLKMODE BIT(28)
55 #define MSS_SPI_CONTROL_BIGFIFO BIT(29)
56 #define MSS_SPI_CONTROL_OENOFF BIT(30)
57 #define MSS_SPI_CONTROL_RESET BIT(31)
58
59 /* SPIFRAMESIZE bit definitions */
60 #define MSS_SPI_FRAMESIZE_DEFAULT (8)
61
62 /* SPISS bit definitions */
63 #define MSS_SPI_SSEL_MASK (0xff)
64 #define MSS_SPI_DIRECT (0x100)
65 #define MSS_SPI_SSELOUT (0x200)
66 #define MSS_SPI_MIN_SLAVE (0)
67 #define MSS_SPI_MAX_SLAVE (7)
68
69 /* SPIST bit definitions */
70 #define MSS_SPI_STATUS_ACTIVE BIT(14)
71 #define MSS_SPI_STATUS_SSEL BIT(13)
72 #define MSS_SPI_STATUS_FRAMESTART BIT(12)
73 #define MSS_SPI_STATUS_TXFIFO_EMPTY_NEXT_READ BIT(11)
74 #define MSS_SPI_STATUS_TXFIFO_EMPTY BIT(10)
75 #define MSS_SPI_STATUS_TXFIFO_FULL_NEXT_WRITE BIT(9)
76 #define MSS_SPI_STATUS_TXFIFO_FULL BIT(8)
77 #define MSS_SPI_STATUS_RXFIFO_EMPTY_NEXT_READ BIT(7)
78 #define MSS_SPI_STATUS_RXFIFO_EMPTY BIT(6)
79 #define MSS_SPI_STATUS_RXFIFO_FULL_NEXT_WRITE BIT(5)
80 #define MSS_SPI_STATUS_RXFIFO_FULL BIT(4)
81 #define MSS_SPI_STATUS_TX_UNDERRUN BIT(3)
82 #define MSS_SPI_STATUS_RX_OVERFLOW BIT(2)
83 #define MSS_SPI_STATUS_RXDAT_RCED BIT(1)
84 #define MSS_SPI_STATUS_TXDAT_SENT BIT(0)
85
86 /* SPIINT register defines */
87 #define MSS_SPI_INT_TXDONE BIT(0)
88 #define MSS_SPI_INT_RXRDY BIT(1)
89 #define MSS_SPI_INT_RX_CH_OVRFLW BIT(2)
90 #define MSS_SPI_INT_TX_CH_UNDRUN BIT(3)
91 #define MSS_SPI_INT_CMD BIT(4)
92 #define MSS_SPI_INT_SSEND BIT(5)
93
94 /* SPICOMMAND bit definitions */
95 #define MSS_SPI_COMMAND_FIFO_MASK (0xC)
96
97 /* SPIFRAMESUP bit definitions */
98 #define MSS_SPI_FRAMESUP_UP_BYTES_MSK (0xFFFF << 16)
99 #define MSS_SPI_FRAMESUP_LO_BYTES_MSK (0xFFFF << 0)
100
101 struct mss_spi_config {
102 mm_reg_t base;
103 uint8_t clk_gen;
104 int clock_freq;
105 };
106
107 struct mss_spi_transfer {
108 uint32_t rx_len;
109 uint32_t control;
110 };
111
112 struct mss_spi_data {
113 struct spi_context ctx;
114 struct mss_spi_transfer xfer;
115 };
116
mss_spi_read(const struct mss_spi_config * cfg,mm_reg_t offset)117 static inline uint32_t mss_spi_read(const struct mss_spi_config *cfg, mm_reg_t offset)
118 {
119 return sys_read32(cfg->base + offset);
120 }
121
mss_spi_write(const struct mss_spi_config * cfg,mm_reg_t offset,uint32_t val)122 static inline void mss_spi_write(const struct mss_spi_config *cfg, mm_reg_t offset, uint32_t val)
123 {
124 sys_write32(val, cfg->base + offset);
125 }
126
mss_spi_hw_tfsz_set(const struct mss_spi_config * cfg,int len)127 static inline void mss_spi_hw_tfsz_set(const struct mss_spi_config *cfg, int len)
128 {
129 uint32_t control;
130
131 mss_spi_write(cfg, MSS_SPI_REG_FRAMESUP, (len & MSS_SPI_FRAMESUP_UP_BYTES_MSK));
132 control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);
133 control &= ~MSS_SPI_CONTROL_CNT_MSK;
134 control |= ((len & MSS_SPI_FRAMESUP_LO_BYTES_MSK) << MSS_SPI_CONTROL_CNT_SHF);
135 mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);
136 }
137
mss_spi_enable_controller(const struct mss_spi_config * cfg)138 static inline void mss_spi_enable_controller(const struct mss_spi_config *cfg)
139 {
140 uint32_t control;
141
142 control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);
143 control |= MSS_SPI_CONTROL_ENABLE;
144 mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);
145 }
146
mss_spi_disable_controller(const struct mss_spi_config * cfg)147 static inline void mss_spi_disable_controller(const struct mss_spi_config *cfg)
148 {
149 uint32_t control;
150
151 control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);
152 control &= ~MSS_SPI_CONTROL_ENABLE;
153 mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);
154 }
155
mss_spi_enable_ints(const struct mss_spi_config * cfg)156 static void mss_spi_enable_ints(const struct mss_spi_config *cfg)
157 {
158 uint32_t control;
159 uint32_t mask = MSS_SPI_CONTROL_RX_DATA_INT | MSS_SPI_CONTROL_TX_DATA_INT |
160 MSS_SPI_CONTROL_RX_OVER_INT | MSS_SPI_CONTROL_TX_UNDER_INT;
161
162 control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);
163 control |= mask;
164 mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);
165 }
166
mss_spi_disable_ints(const struct mss_spi_config * cfg)167 static void mss_spi_disable_ints(const struct mss_spi_config *cfg)
168 {
169 uint32_t control;
170 uint32_t mask = MSS_SPI_CONTROL_RX_DATA_INT | MSS_SPI_CONTROL_TX_DATA_INT |
171 MSS_SPI_CONTROL_RX_OVER_INT | MSS_SPI_CONTROL_TX_UNDER_INT;
172
173 mask = ~mask;
174 control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);
175 control &= ~mask;
176 mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);
177 }
178
mss_spi_readwr_fifo(const struct device * dev)179 static inline void mss_spi_readwr_fifo(const struct device *dev)
180 {
181 const struct mss_spi_config *cfg = dev->config;
182 struct mss_spi_data *data = dev->data;
183 struct spi_context *ctx = &data->ctx;
184 struct mss_spi_transfer *xfer = &data->xfer;
185 uint32_t rx_raw = 0, rd_byte_size, tr_len;
186 uint32_t data8, transfer_idx = 0;
187 int count;
188
189 tr_len = spi_context_longest_current_buf(ctx);
190 count = spi_context_total_tx_len(ctx);
191 if (ctx->rx_buf) {
192 rd_byte_size = count - tr_len;
193 } else {
194 rd_byte_size = 0;
195 }
196 mss_spi_hw_tfsz_set(cfg, count);
197
198 mss_spi_enable_ints(cfg);
199 spi_context_update_rx(ctx, 1, xfer->rx_len);
200 while (transfer_idx < count) {
201 if (!(mss_spi_read(cfg, MSS_SPI_REG_STATUS) & MSS_SPI_STATUS_RXFIFO_EMPTY)) {
202 rx_raw = mss_spi_read(cfg, MSS_SPI_REG_RX_DATA);
203 if (transfer_idx >= tr_len) {
204 if (spi_context_rx_buf_on(ctx)) {
205 UNALIGNED_PUT(rx_raw, (uint8_t *)ctx->rx_buf);
206 spi_context_update_rx(ctx, 1, 1);
207 }
208 }
209 ++transfer_idx;
210 }
211
212 if (!(mss_spi_read(cfg, MSS_SPI_REG_STATUS) & MSS_SPI_STATUS_TXFIFO_FULL)) {
213 if (spi_context_tx_buf_on(ctx)) {
214 data8 = ctx->tx_buf[0];
215 mss_spi_write(cfg, MSS_SPI_REG_TX_DATA, data8);
216 spi_context_update_tx(ctx, 1, 1);
217 } else {
218 mss_spi_write(cfg, MSS_SPI_REG_TX_DATA, 0x0);
219 }
220 }
221 }
222 }
223
mss_spi_select_slave(const struct mss_spi_config * cfg,int cs)224 static inline int mss_spi_select_slave(const struct mss_spi_config *cfg, int cs)
225 {
226 uint32_t slave;
227 uint32_t reg = mss_spi_read(cfg, MSS_SPI_REG_SS);
228
229 slave = (cs >= MSS_SPI_MIN_SLAVE && cs <= MSS_SPI_MAX_SLAVE) ? (1 << cs) : 0;
230 reg &= ~MSS_SPI_SSEL_MASK;
231 reg |= slave;
232
233 mss_spi_write(cfg, MSS_SPI_REG_SS, reg);
234
235 return 0;
236 }
237
mss_spi_activate_cs(struct mss_spi_config * cfg)238 static inline void mss_spi_activate_cs(struct mss_spi_config *cfg)
239 {
240 uint32_t reg = mss_spi_read(cfg, MSS_SPI_REG_SS);
241
242 reg |= MSS_SPI_SSELOUT;
243 mss_spi_write(cfg, MSS_SPI_REG_SS, reg);
244 }
245
mss_spi_deactivate_cs(const struct mss_spi_config * cfg)246 static inline void mss_spi_deactivate_cs(const struct mss_spi_config *cfg)
247 {
248 uint32_t reg = mss_spi_read(cfg, MSS_SPI_REG_SS);
249
250 reg &= ~MSS_SPI_SSELOUT;
251 mss_spi_write(cfg, MSS_SPI_REG_SS, reg);
252 }
253
mss_spi_clk_gen_set(const struct mss_spi_config * cfg,const struct spi_config * spi_cfg)254 static inline int mss_spi_clk_gen_set(const struct mss_spi_config *cfg,
255 const struct spi_config *spi_cfg)
256 {
257 uint32_t idx, clkrate, val = 0, speed;
258
259 if (spi_cfg->frequency > cfg->clock_freq) {
260 speed = cfg->clock_freq / 2;
261 }
262
263 for (idx = 1; idx < 16; idx++) {
264 clkrate = cfg->clock_freq / (2 * idx);
265 if (clkrate <= spi_cfg->frequency) {
266 val = idx;
267 break;
268 }
269 }
270
271 mss_spi_write(cfg, MSS_SPI_REG_CLK_GEN, val);
272
273 return 0;
274 }
275
mss_spi_hw_mode_set(const struct mss_spi_config * cfg,unsigned int mode)276 static inline int mss_spi_hw_mode_set(const struct mss_spi_config *cfg, unsigned int mode)
277 {
278 uint32_t control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);
279
280 /* set the mode */
281 if (mode & SPI_MODE_CPHA) {
282 control |= MSS_SPI_CONTROL_SPH;
283 } else {
284 control &= ~MSS_SPI_CONTROL_SPH;
285 }
286
287 if (mode & SPI_MODE_CPOL) {
288 control |= MSS_SPI_CONTROL_SPO;
289 } else {
290 control &= ~MSS_SPI_CONTROL_SPO;
291 }
292
293 mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);
294
295 return 0;
296 }
297
mss_spi_interrupt(const struct device * dev)298 static void mss_spi_interrupt(const struct device *dev)
299 {
300 const struct mss_spi_config *cfg = dev->config;
301 struct mss_spi_data *data = dev->data;
302 struct spi_context *ctx = &data->ctx;
303 int intfield = mss_spi_read(cfg, MSS_SPI_REG_MIS) & 0xf;
304
305 if (intfield == 0) {
306 return;
307 }
308
309 mss_spi_write(cfg, MSS_SPI_REG_INT_CLEAR, intfield);
310 spi_context_complete(ctx, dev, 0);
311 }
312
mss_spi_release(const struct device * dev,const struct spi_config * config)313 static int mss_spi_release(const struct device *dev, const struct spi_config *config)
314 {
315 const struct mss_spi_config *cfg = dev->config;
316 struct mss_spi_data *data = dev->data;
317
318 mss_spi_disable_ints(cfg);
319
320 /* release kernel resources */
321 spi_context_unlock_unconditionally(&data->ctx);
322 mss_spi_disable_controller(cfg);
323
324 return 0;
325 }
326
mss_spi_configure(const struct device * dev,const struct spi_config * spi_cfg)327 static int mss_spi_configure(const struct device *dev, const struct spi_config *spi_cfg)
328 {
329 const struct mss_spi_config *cfg = dev->config;
330 struct mss_spi_data *data = dev->data;
331 struct spi_context *ctx = &data->ctx;
332 struct mss_spi_transfer *xfer = &data->xfer;
333 uint32_t control;
334
335 if (spi_cfg->operation & (SPI_TRANSFER_LSB | SPI_OP_MODE_SLAVE | SPI_MODE_LOOP)) {
336 LOG_WRN("not supported operation\n\r");
337 return -ENOTSUP;
338 }
339
340 if (SPI_WORD_SIZE_GET(spi_cfg->operation) != MSS_SPI_FRAMESIZE_DEFAULT) {
341 return -ENOTSUP;
342 }
343
344 ctx->config = spi_cfg;
345 mss_spi_select_slave(cfg, spi_cfg->slave);
346 control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);
347
348 /*
349 * Fill up the default values
350 * Slave select behaviour set
351 * Fifo depth greater than 4 frames
352 * Methodology to calculate SPI Clock:
353 * 0: SPICLK = 1 / (2 CLK_GEN + 1) , CLK_GEN is from 0 to 15
354 * 1: SPICLK = 1 / (2 * (CLK_GEN + 1)) , CLK_GEN is from 0 to 255
355 */
356
357 mss_spi_write(cfg, MSS_SPI_REG_CONTROL, xfer->control);
358
359 if (mss_spi_clk_gen_set(cfg, spi_cfg)) {
360 LOG_ERR("can't set clk divider\n");
361 return -EINVAL;
362 }
363
364 mss_spi_hw_mode_set(cfg, spi_cfg->operation);
365 mss_spi_write(cfg, MSS_SPI_REG_TXRXDF_SIZE, MSS_SPI_FRAMESIZE_DEFAULT);
366 mss_spi_enable_controller(cfg);
367 mss_spi_write(cfg, MSS_SPI_REG_COMMAND, MSS_SPI_COMMAND_FIFO_MASK);
368
369 return 0;
370 }
371
mss_spi_transceive(const struct device * dev,const struct spi_config * spi_cfg,const struct spi_buf_set * tx_bufs,const struct spi_buf_set * rx_bufs,bool async,spi_callback_t cb,void * userdata)372 static int mss_spi_transceive(const struct device *dev, const struct spi_config *spi_cfg,
373 const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs,
374 bool async, spi_callback_t cb, void *userdata)
375 {
376
377 const struct mss_spi_config *config = dev->config;
378 struct mss_spi_data *data = dev->data;
379 struct spi_context *ctx = &data->ctx;
380 struct mss_spi_transfer *xfer = &data->xfer;
381 int ret = 0;
382
383 spi_context_lock(ctx, async, cb, userdata, spi_cfg);
384
385 ret = mss_spi_configure(dev, spi_cfg);
386 if (ret) {
387 LOG_ERR("Fail to configure\n\r");
388 goto out;
389 }
390
391 spi_context_buffers_setup(ctx, tx_bufs, rx_bufs, 1);
392 xfer->rx_len = ctx->rx_len;
393 mss_spi_readwr_fifo(dev);
394 ret = spi_context_wait_for_completion(ctx);
395 out:
396 spi_context_release(ctx, ret);
397 mss_spi_disable_ints(config);
398 mss_spi_disable_controller(config);
399
400 return ret;
401 }
402
mss_spi_transceive_blocking(const struct device * dev,const struct spi_config * spi_cfg,const struct spi_buf_set * tx_bufs,const struct spi_buf_set * rx_bufs)403 static int mss_spi_transceive_blocking(const struct device *dev, const struct spi_config *spi_cfg,
404 const struct spi_buf_set *tx_bufs,
405 const struct spi_buf_set *rx_bufs)
406 {
407
408 return mss_spi_transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL);
409 }
410
411 #ifdef CONFIG_SPI_ASYNC
mss_spi_transceive_async(const struct device * dev,const struct spi_config * spi_cfg,const struct spi_buf_set * tx_bufs,const struct spi_buf_set * rx_bufs,spi_callback_t cb,void * userdata)412 static int mss_spi_transceive_async(const struct device *dev, const struct spi_config *spi_cfg,
413 const struct spi_buf_set *tx_bufs,
414 const struct spi_buf_set *rx_bufs, spi_callback_t cb,
415 void *userdata)
416 {
417 return mss_spi_transceive(dev, spi_cfg, tx_bufs, rx_bufs, true, cb, userdata);
418 }
419 #endif /* CONFIG_SPI_ASYNC */
420
mss_spi_init(const struct device * dev)421 static int mss_spi_init(const struct device *dev)
422 {
423 const struct mss_spi_config *cfg = dev->config;
424 struct mss_spi_data *data = dev->data;
425 struct mss_spi_transfer *xfer = &data->xfer;
426 int ret = 0;
427 uint32_t control = 0;
428
429 /* Remove SPI from Reset */
430 control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);
431 control &= ~MSS_SPI_CONTROL_RESET;
432 mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);
433
434 /* Set master mode */
435 mss_spi_disable_controller(cfg);
436 xfer->control = (MSS_SPI_CONTROL_SPS | MSS_SPI_CONTROL_BIGFIFO | MSS_SPI_CONTROL_MASTER |
437 MSS_SPI_CONTROL_CLKMODE);
438
439 spi_context_unlock_unconditionally(&data->ctx);
440
441 return ret;
442 }
443
444 #define MICROCHIP_SPI_PM_OPS (NULL)
445
446 static DEVICE_API(spi, mss_spi_driver_api) = {
447 .transceive = mss_spi_transceive_blocking,
448 #ifdef CONFIG_SPI_ASYNC
449 .transceive_async = mss_spi_transceive_async,
450 #endif /* CONFIG_SPI_ASYNC */
451 #ifdef CONFIG_SPI_RTIO
452 .iodev_submit = spi_rtio_iodev_default_submit,
453 #endif
454 .release = mss_spi_release,
455 };
456
457 #define MSS_SPI_INIT(n) \
458 static int mss_spi_init_##n(const struct device *dev) \
459 { \
460 mss_spi_init(dev); \
461 \
462 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), mss_spi_interrupt, \
463 DEVICE_DT_INST_GET(n), 0); \
464 \
465 irq_enable(DT_INST_IRQN(n)); \
466 \
467 return 0; \
468 } \
469 \
470 static const struct mss_spi_config mss_spi_config_##n = { \
471 .base = DT_INST_REG_ADDR(n), \
472 .clock_freq = DT_INST_PROP(n, clock_frequency), \
473 }; \
474 \
475 static struct mss_spi_data mss_spi_data_##n = { \
476 SPI_CONTEXT_INIT_LOCK(mss_spi_data_##n, ctx), \
477 SPI_CONTEXT_INIT_SYNC(mss_spi_data_##n, ctx), \
478 }; \
479 \
480 SPI_DEVICE_DT_INST_DEFINE(n, mss_spi_init_##n, NULL, &mss_spi_data_##n, \
481 &mss_spi_config_##n, POST_KERNEL, \
482 CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &mss_spi_driver_api);
483
484 DT_INST_FOREACH_STATUS_OKAY(MSS_SPI_INIT)
485
