1 /* Copyright 2023 The ChromiumOS Authors
2 * SPDX-License-Identifier: Apache-2.0
3 */
4 #include <zephyr/arch/cpu.h>
5 #include <zephyr/device.h>
6
7 #define DT_DRV_COMPAT mediatek_adsp_intc
8
9 struct intc_mtk_cfg {
10 uint32_t xtensa_irq;
11 uint32_t irq_mask;
12 uint32_t sw_isr_off;
13 volatile uint32_t *enable_reg;
14 volatile uint32_t *status_reg;
15 };
16
intc_mtk_adsp_get_enable(const struct device * dev,int irq)17 bool intc_mtk_adsp_get_enable(const struct device *dev, int irq)
18 {
19 const struct intc_mtk_cfg *cfg = dev->config;
20
21 return (*cfg->enable_reg | (BIT(irq) & cfg->irq_mask)) != 0;
22 }
23
intc_mtk_adsp_set_enable(const struct device * dev,int irq,bool val)24 void intc_mtk_adsp_set_enable(const struct device *dev, int irq, bool val)
25 {
26 const struct intc_mtk_cfg *cfg = dev->config;
27
28 irq_enable(cfg->xtensa_irq);
29
30 if ((BIT(irq) & cfg->irq_mask) != 0) {
31 if (val) {
32 *cfg->enable_reg |= BIT(irq);
33 } else {
34 *cfg->enable_reg &= ~BIT(irq);
35 }
36 }
37 }
38
intc_isr(const void * arg)39 static void intc_isr(const void *arg)
40 {
41 const struct intc_mtk_cfg *cfg = ((struct device *)arg)->config;
42 uint32_t irqs = *cfg->status_reg & cfg->irq_mask;
43
44 while (irqs != 0) {
45 uint32_t irq = find_msb_set(irqs) - 1;
46 uint32_t off = cfg->sw_isr_off + irq;
47
48 _sw_isr_table[off].isr(_sw_isr_table[off].arg);
49 irqs &= ~BIT(irq);
50 }
51 }
52
dev_init(const struct device * dev)53 static void dev_init(const struct device *dev)
54 {
55 const struct intc_mtk_cfg *cfg = dev->config;
56
57 *cfg->enable_reg = 0;
58 irq_enable(cfg->xtensa_irq);
59 }
60
61 #define DEV_INIT(N) \
62 IRQ_CONNECT(DT_INST_IRQN(N), 0, intc_isr, DEVICE_DT_INST_GET(N), 0); \
63 dev_init(DEVICE_DT_INST_GET(N));
64
intc_init(void)65 static int intc_init(void)
66 {
67 DT_INST_FOREACH_STATUS_OKAY(DEV_INIT);
68 return 0;
69 }
70
71 SYS_INIT(intc_init, PRE_KERNEL_1, 0);
72
73 #define DEF_DEV(N) \
74 static const struct intc_mtk_cfg dev_cfg##N = { \
75 .xtensa_irq = DT_INST_IRQN(N), \
76 .irq_mask = DT_INST_PROP(N, mask), \
77 .sw_isr_off = (N + 1) * 32, \
78 .enable_reg = (void *)DT_INST_REG_ADDR(N), \
79 .status_reg = (void *)DT_INST_PROP(N, status_reg) }; \
80 DEVICE_DT_INST_DEFINE(N, NULL, NULL, NULL, &dev_cfg##N, PRE_KERNEL_1, 0, NULL);
81
82 DT_INST_FOREACH_STATUS_OKAY(DEF_DEV);
83
