117 static inline uint32_t mss_spi_read(const struct mss_spi_config *cfg, mm_reg_t offset)  in mss_spi_read()  argument
119 	return sys_read32(cfg->base + offset);  in mss_spi_read()
122 static inline void mss_spi_write(const struct mss_spi_config *cfg, mm_reg_t offset, uint32_t val)  in mss_spi_write()  argument
124 	sys_write32(val, cfg->base + offset);  in mss_spi_write()
127 static inline void mss_spi_hw_tfsz_set(const struct mss_spi_config *cfg, int len)  in mss_spi_hw_tfsz_set()  argument
131 	mss_spi_write(cfg, MSS_SPI_REG_FRAMESUP, (len & MSS_SPI_FRAMESUP_UP_BYTES_MSK));  in mss_spi_hw_tfsz_set()
132 	control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);  in mss_spi_hw_tfsz_set()
135 	mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);  in mss_spi_hw_tfsz_set()
138 static inline void mss_spi_enable_controller(const struct mss_spi_config *cfg)  in mss_spi_enable_controller()  argument
142 	control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);  in mss_spi_enable_controller()
144 	mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);  in mss_spi_enable_controller()
147 static inline void mss_spi_disable_controller(const struct mss_spi_config *cfg)  in mss_spi_disable_controller()  argument
151 	control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);  in mss_spi_disable_controller()
153 	mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);  in mss_spi_disable_controller()
156 static void mss_spi_enable_ints(const struct mss_spi_config *cfg)  in mss_spi_enable_ints()  argument
162 	control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);  in mss_spi_enable_ints()
164 	mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);  in mss_spi_enable_ints()
167 static void mss_spi_disable_ints(const struct mss_spi_config *cfg)  in mss_spi_disable_ints()  argument
174 	control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);  in mss_spi_disable_ints()
176 	mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);  in mss_spi_disable_ints()
181 	const struct mss_spi_config *cfg = dev->config;  in mss_spi_readwr_fifo()  local
196 	mss_spi_hw_tfsz_set(cfg, count);  in mss_spi_readwr_fifo()
198 	mss_spi_enable_ints(cfg);  in mss_spi_readwr_fifo()
201 		if (!(mss_spi_read(cfg, MSS_SPI_REG_STATUS) & MSS_SPI_STATUS_RXFIFO_EMPTY)) {  in mss_spi_readwr_fifo()
202 			rx_raw = mss_spi_read(cfg, MSS_SPI_REG_RX_DATA);  in mss_spi_readwr_fifo()
212 		if (!(mss_spi_read(cfg, MSS_SPI_REG_STATUS) & MSS_SPI_STATUS_TXFIFO_FULL)) {  in mss_spi_readwr_fifo()
215 				mss_spi_write(cfg, MSS_SPI_REG_TX_DATA, data8);  in mss_spi_readwr_fifo()
218 				mss_spi_write(cfg, MSS_SPI_REG_TX_DATA, 0x0);  in mss_spi_readwr_fifo()
224 static inline int mss_spi_select_slave(const struct mss_spi_config *cfg, int cs)  in mss_spi_select_slave()  argument
227 	uint32_t reg = mss_spi_read(cfg, MSS_SPI_REG_SS);  in mss_spi_select_slave()
233 	mss_spi_write(cfg, MSS_SPI_REG_SS, reg);  in mss_spi_select_slave()
238 static inline void mss_spi_activate_cs(struct mss_spi_config *cfg)  in mss_spi_activate_cs()  argument
240 	uint32_t reg = mss_spi_read(cfg, MSS_SPI_REG_SS);  in mss_spi_activate_cs()
243 	mss_spi_write(cfg, MSS_SPI_REG_SS, reg);  in mss_spi_activate_cs()
246 static inline void mss_spi_deactivate_cs(const struct mss_spi_config *cfg)  in mss_spi_deactivate_cs()  argument
248 	uint32_t reg = mss_spi_read(cfg, MSS_SPI_REG_SS);  in mss_spi_deactivate_cs()
251 	mss_spi_write(cfg, MSS_SPI_REG_SS, reg);  in mss_spi_deactivate_cs()
254 static inline int mss_spi_clk_gen_set(const struct mss_spi_config *cfg,  in mss_spi_clk_gen_set()  argument
259 	if (spi_cfg->frequency > cfg->clock_freq) {  in mss_spi_clk_gen_set()
260 		speed = cfg->clock_freq / 2;  in mss_spi_clk_gen_set()
264 		clkrate = cfg->clock_freq / (2 * idx);  in mss_spi_clk_gen_set()
271 	mss_spi_write(cfg, MSS_SPI_REG_CLK_GEN, val);  in mss_spi_clk_gen_set()
276 static inline int mss_spi_hw_mode_set(const struct mss_spi_config *cfg, unsigned int mode)  in mss_spi_hw_mode_set()  argument
278 	uint32_t control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);  in mss_spi_hw_mode_set()
293 	mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);  in mss_spi_hw_mode_set()
300 	const struct mss_spi_config *cfg = dev->config;  in mss_spi_interrupt()  local
303 	int intfield = mss_spi_read(cfg, MSS_SPI_REG_MIS) & 0xf;  in mss_spi_interrupt()
309 	mss_spi_write(cfg, MSS_SPI_REG_INT_CLEAR, intfield);  in mss_spi_interrupt()
315 	const struct mss_spi_config *cfg = dev->config;  in mss_spi_release()  local
318 	mss_spi_disable_ints(cfg);  in mss_spi_release()
322 	mss_spi_disable_controller(cfg);  in mss_spi_release()
329 	const struct mss_spi_config *cfg = dev->config;  in mss_spi_configure()  local
345 	mss_spi_select_slave(cfg, spi_cfg->slave);  in mss_spi_configure()
346 	control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);  in mss_spi_configure()
357 	mss_spi_write(cfg, MSS_SPI_REG_CONTROL, xfer->control);  in mss_spi_configure()
359 	if (mss_spi_clk_gen_set(cfg, spi_cfg)) {  in mss_spi_configure()
364 	mss_spi_hw_mode_set(cfg, spi_cfg->operation);  in mss_spi_configure()
365 	mss_spi_write(cfg, MSS_SPI_REG_TXRXDF_SIZE, MSS_SPI_FRAMESIZE_DEFAULT);  in mss_spi_configure()
366 	mss_spi_enable_controller(cfg);  in mss_spi_configure()
367 	mss_spi_write(cfg, MSS_SPI_REG_COMMAND, MSS_SPI_COMMAND_FIFO_MASK);  in mss_spi_configure()
423 	const struct mss_spi_config *cfg = dev->config;  in mss_spi_init()  local
430 	control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL);  in mss_spi_init()
432 	mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);  in mss_spi_init()
435 	mss_spi_disable_controller(cfg);  in mss_spi_init()