Home
last modified time | relevance | path

Searched +full:aggregated +full:- +full:girq (Results 1 – 14 of 14) sorted by relevance

/Zephyr-latest/drivers/interrupt_controller/
Dintc_mchp_ecia_xec.c4 * SPDX-License-Identifier: Apache-2.0
22 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
72 ((const struct xec_ecia_config *const)(ecia_dev)->config)
75 ((const struct xec_girq_config *const)(girq_dev)->config)
78 ((struct xec_girq_src_data *const)(girq_dev)->data)
81 * Enable/disable specified GIRQ's aggregated output. Aggregated output is the
82 * bit-wise or of all the GIRQ's result bits.
89 regs->BLK_EN_SET = BIT(girq_num); in mchp_xec_ecia_girq_aggr_en()
91 regs->BLK_EN_CLR = BIT(girq_num); in mchp_xec_ecia_girq_aggr_en()
104 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].SRC = BIT(src_bit_pos); in mchp_xec_ecia_girq_src_clr()
[all …]
/Zephyr-latest/dts/bindings/dma/
Dmicrochip,xec-dmac.yaml3 compatible: "microchip,xec-dmac"
5 include: dma-controller.yaml
24 aggregated-girq:
27 If DMA driver uses aggregated interrupt mode
28 provide the handle to the GIRQ.
30 "#dma-cells":
33 "pcr-cells":
37 "girq-cells":
41 # #dma-cells : Must be <2>.
55 # dma-names = "rx", "tx";
[all …]
/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Dintc_mchp_xec_ecia.h4 * SPDX-License-Identifier: Apache-2.0
11 * Reference Manuals for MEC152x and MEC172x ARM(r) 32-bit MCUs
26 * @param girq_id is the GIRQ number (8 - 26)
27 * @param src is the interrupt source in the GIRQ (0 - 31)
35 * @param ecia_info is GIRQ connection encoded with MCHP_XEC_ECIA
42 * @param girq_id is the GIRQ number (8 - 26)
43 * @param src is the interrupt source in the GIRQ (0 - 31)
51 * @param ecia_info is GIRQ connection encoded with MCHP_XEC_ECIA
56 /* callback for ECIA GIRQ interrupt source */
62 * @param girq_id is the GIRQ number (8 - 26)
[all …]
/Zephyr-latest/dts/bindings/spi/
Dmicrochip,xec-qmspi-ldma.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "microchip,xec-qmspi-ldma"
9 include: [spi-controller.yaml, pinctrl-device.yaml]
26 This information includes the aggregated GIRQ number, GIRQ bit
27 position, aggregated GIRQ NVIC connection, and direct NVIC
28 connection of the GIRQ bit.
30 pinctrl-0:
33 pinctrl-names:
39 QMSPI data lines 1, 2, or 4. 1 data line is full-duplex
40 MOSI and MISO or half-duplex on MOSI only. Lines set to 2
[all …]
/Zephyr-latest/dts/bindings/gpio/
Dmicrochip,xec-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-gpio"
8 include: [gpio-controller.yaml, base.yaml]
14 port-id:
19 girq-id:
22 description: Aggregated GIRQ number for this bank of 32 GPIO pins.
24 "#gpio-cells":
27 gpio-cells:
28 - pin
29 - flags
Dmicrochip,xec-gpio-v2.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-gpio-v2"
8 include: [gpio-controller.yaml, base.yaml]
14 port-id:
19 girq-id:
22 description: Aggregated GIRQ number for this bank of 32 GPIO pins.
24 "#gpio-cells":
27 gpio-cells:
28 - pin
29 - flags
/Zephyr-latest/dts/bindings/espi/
Dmicrochip,xec-espi-vw-routing.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-espi-vw-routing"
10 child-binding:
13 VW registers and ECIA GIRQ registers.
15 vw-reg:
20 vw-girq:
23 Routing of MSVW source to aggregated GIRQs
26 to GIRQ24 b[5]. vw-girq = <24 5>;
28 reset-state:
34 - "HW_DFLT"
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Dmchp-xec-ecia.h4 * SPDX-License-Identifier: Apache-2.0
10 * Encode peripheral interrupt information into a 32-bit unsigned.
11 * g = bits[0:4], GIRQ number in [8, 26]
12 * gb = bits[12:8], peripheral source bit position [0, 31] in the GIRQ
13 * na = bits[23:16], aggregated GIRQ NVIC number
/Zephyr-latest/drivers/espi/
Despi_mchp_xec_v2.h4 * SPDX-License-Identifier: Apache-2.0
27 void (*the_isr)(int girq, int bpos, void *dev);
31 uint8_t gid; /* GIRQ id [8, 26] */
32 uint8_t gpos; /* bit position in GIRQ [0, 31] */
33 uint8_t anid; /* Aggregated GIRQ NVIC number */
34 uint8_t dnid; /* Direct GIRQ NVIC number */
49 ((struct espi_xec_config * const)(dev)->config)
62 ((struct espi_xec_data * const)(dev)->data)
Despi_mchp_xec_v2.c5 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
40 * length specified is non-zero.
61 ((struct espi_iom_regs *)ESPI_XEC_CONFIG(dev)->base_addr)
64 ((struct espi_msvw_ar_regs *)(ESPI_XEC_CONFIG(dev)->vw_base_addr))
70 (ESPI_XEC_CONFIG(dev)->vw_base_addr + ESPI_XEC_SMVW_REG_OFS))
77 * ------------------------------------------------------------------------|
79 * ------------------------------------------------------------------------|
81 * ------------------------------------------------------------------------|
88 * ------------------------------------------------------------------------|
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_ecia.h4 * SPDX-License-Identifier: Apache-2.0
40 * ARM Cortex-M4 NVIC registers
41 * External sources are grouped by 32-bit registers.
42 * MEC172x has 181 external sources requiring 6 32-bit registers.
54 * Implements 19 GIRQ's. GIRQ's aggregated interrupts source into one
56 * For historical reason GIRQ's are numbered starting at 8 in the documentation.
60 * Each GIRQ is composed of 5 32-bit registers.
63 * +08h = Read-Only Result = Source AND Enable-Set
69 * 0x200: BLOCK_EN_SET bit == 1 connects bit-wise OR of all GIRQn result
72 * 0x204: BLOCK_EN_CLR bit == 1 disconnects bit-wise OR of GIRQn source
[all …]
/Zephyr-latest/soc/microchip/mec/mec15xx/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
26 ECS_REGS->INTR_CTRL |= MCHP_ECS_ICTRL_DIRECT_EN; in soc_ecia_init()
28 /* gate off all aggregated outputs */ in soc_ecia_init()
29 ECIA_REGS->BLK_EN_CLR = 0xFFFFFFFFul; in soc_ecia_init()
30 /* gate on GIRQ's that are aggregated only */ in soc_ecia_init()
31 ECIA_REGS->BLK_EN_SET = MCHP_ECIA_AGGR_BITMAP; in soc_ecia_init()
34 pg = &ECIA_REGS->GIRQ08; in soc_ecia_init()
36 pg->EN_CLR = 0xFFFFFFFFul; in soc_ecia_init()
37 pg->SRC = 0xFFFFFFFFul; in soc_ecia_init()
43 NVIC->ICER[n] = 0xFFFFFFFFul; in soc_ecia_init()
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
14 * eight regions. Zephyr has an in-tree CMSIS header located in the arch
16 * from hal_cmsis based on the k-config CPU selection.
17 * The Zephyr in-tree header does not provide all the symbols ARM CMSIS
19 * MPU present to 0. We define these two symbols here based on our k-config
20 * selections. NOTE: Zephyr in-tree CMSIS defines the Cortex-M4 hardware
33 #define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */
34 #define __DCACHE_PRESENT 0 /*!< Set to 1 if D-Cache is present */
37 /** @brief ARM Cortex-M4 NVIC Interrupt Numbers
39 * negative numbers [-15, -1]. Lower numerical value indicates higher
[all …]
/Zephyr-latest/drivers/dma/
Ddma_mchp_xec.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
105 uint8_t gid; /* GIRQ id [8, 26] */
106 uint8_t gpos; /* bit position in GIRQ [0, 31] */
107 uint8_t anid; /* aggregated external NVIC input */
166 return &devcfg->irq_info_list[channel]; in xec_chan_irq_info()
187 if ((src | dest) & (unitsz - 1U)) { in is_data_aligned()
197 chregs->actv = 0; in xec_dma_chan_clr()
198 chregs->control = 0; in xec_dma_chan_clr()
199 chregs->mem_addr = 0; in xec_dma_chan_clr()
[all …]