4  * SPDX-License-Identifier: Apache-2.0
40  * ARM Cortex-M4 NVIC registers
41  * External sources are grouped by 32-bit registers.
42  * MEC172x has 181 external sources requiring 6 32-bit registers.
54  * Implements 19 GIRQ's. GIRQ's aggregated interrupts source into one
56  * For historical reason GIRQ's are numbered starting at 8 in the documentation.
60  * Each GIRQ is composed of 5 32-bit registers.
63  * +08h = Read-Only Result = Source AND Enable-Set
69  * 0x200: BLOCK_EN_SET bit == 1 connects bit-wise OR of all GIRQn result
72  * 0x204: BLOCK_EN_CLR bit == 1 disconnects bit-wise OR of GIRQn source
74  * 0x208: BLOCK_ACTIVE (read-only)
78  * The aggregated (bit-wise OR) of GIRQ08, ..., GIRQ26 are connected to NVIC
80  * wake. If GIRQ22 sources are enabled activity on a source will re-enable the
85  * re-enter deep sleep.
86  * Aggregated GIRQ NVIC mapping:
87  * GIRQ08 -> NVIC 0
88  * GIRQ09 -> NVIC 1
90  * GIRQ21 -> NVIC 13
92  * GIRQ23 -> NVIC 14
94  * GIRQ26 -> NVIC 17
95  * NVIC 20 and above are direct mode(not aggregated) connections.
96  * Result bits in GIRQ's 13 - 21, and 23 can be directly connected to NVIC
126 /* zero based index into ECIA_Type GIRQ[] */
807  * enabled GIRQ20 must be used in aggregated mode.
952  * If RTMR SWI will be used GIRQ23 must be aggregated.
1118 /* GIRQ numbering */
1121 #define MCHP_GIRQ_IDX(girq)	((uint32_t)(girq) - 8u)  argument
1124 /* Number of NVIC Enable_Set/Clr, Pending_Set/Clr, Active 32-bit registers */
1129 /** @brief GIRQ registers. Total size = 20(0x14) bytes */
1138 /** @brief ECIA registers with each GIRQ elucidated */
1159 	uint8_t RSVD2[(0x0200 - 0x017c)];
1165 /** @brief ECIA registers with array of GIRQ's */
1167 	struct girq_regs GIRQ[19];  member
1168 	uint8_t RSVD2[(0x200 - 0x17c)];
1175 static inline void mchp_soc_ecia_girq_aggr_en(uint8_t girq, uint8_t en)  in mchp_soc_ecia_girq_aggr_en()  argument
1177 	if ((girq < MCHP_FIRST_GIRQ_NOS) || (girq > MCHP_LAST_GIRQ_NOS)) {  in mchp_soc_ecia_girq_aggr_en()
1184 		ecia->BLK_EN_SET = BIT(girq);  in mchp_soc_ecia_girq_aggr_en()
1186 		ecia->BLK_EN_CLR = BIT(girq);  in mchp_soc_ecia_girq_aggr_en()
1190 static inline void mchp_soc_ecia_girq_src_clr(uint8_t girq, uint8_t pin)  in mchp_soc_ecia_girq_src_clr()  argument
1192 	if ((girq < MCHP_FIRST_GIRQ_NOS) || (girq > MCHP_LAST_GIRQ_NOS) ||  in mchp_soc_ecia_girq_src_clr()
1199 	ecia->GIRQ[girq - 8u].SRC = BIT(pin);  in mchp_soc_ecia_girq_src_clr()
1202 static inline void mchp_soc_ecia_girq_src_clr_bitmap(uint8_t girq,  in mchp_soc_ecia_girq_src_clr_bitmap()  argument
1205 	if ((girq < MCHP_FIRST_GIRQ_NOS) || (girq > MCHP_LAST_GIRQ_NOS)) {  in mchp_soc_ecia_girq_src_clr_bitmap()
1211 	ecia->GIRQ[girq - 8u].SRC = bitmap;  in mchp_soc_ecia_girq_src_clr_bitmap()
1214 static inline void mchp_soc_ecia_girq_src_dis(uint8_t girq, uint8_t pin)  in mchp_soc_ecia_girq_src_dis()  argument
1216 	if ((girq < MCHP_FIRST_GIRQ_NOS) || (girq > MCHP_LAST_GIRQ_NOS) ||  in mchp_soc_ecia_girq_src_dis()
1223 	ecia->GIRQ[girq - 8u].EN_CLR = BIT(pin);  in mchp_soc_ecia_girq_src_dis()
1226 static inline void mchp_soc_ecia_girq_src_en(uint8_t girq, uint8_t pin)  in mchp_soc_ecia_girq_src_en()  argument
1228 	if ((girq < MCHP_FIRST_GIRQ_NOS) || (girq > MCHP_LAST_GIRQ_NOS) ||  in mchp_soc_ecia_girq_src_en()
1235 	ecia->GIRQ[girq - 8u].EN_SET = BIT(pin);  in mchp_soc_ecia_girq_src_en()
1238 static inline uint32_t mchp_soc_ecia_girq_result(uint8_t girq)  in mchp_soc_ecia_girq_result()  argument
1240 	if ((girq < MCHP_FIRST_GIRQ_NOS) || (girq > MCHP_LAST_GIRQ_NOS)) {  in mchp_soc_ecia_girq_result()
1246 	return ecia->GIRQ[girq - 8u].RESULT;  in mchp_soc_ecia_girq_result()