Lines Matching +full:aggregated +full:- +full:girq

4  * SPDX-License-Identifier: Apache-2.0
22 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
72 ((const struct xec_ecia_config *const)(ecia_dev)->config)
75 ((const struct xec_girq_config *const)(girq_dev)->config)
78 ((struct xec_girq_src_data *const)(girq_dev)->data)
81 * Enable/disable specified GIRQ's aggregated output. Aggregated output is the
82 * bit-wise or of all the GIRQ's result bits.
89 regs->BLK_EN_SET = BIT(girq_num); in mchp_xec_ecia_girq_aggr_en()
91 regs->BLK_EN_CLR = BIT(girq_num); in mchp_xec_ecia_girq_aggr_en()
104 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].SRC = BIT(src_bit_pos); in mchp_xec_ecia_girq_src_clr()
116 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].EN_SET = BIT(src_bit_pos); in mchp_xec_ecia_girq_src_en()
128 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].EN_CLR = BIT(src_bit_pos); in mchp_xec_ecia_girq_src_dis()
140 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].SRC = bitmap; in mchp_xec_ecia_girq_src_clr_bitmap()
152 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].EN_SET = bitmap; in mchp_xec_ecia_girq_src_en_bitmap()
164 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].EN_CLR = bitmap; in mchp_xec_ecia_girq_src_dis_bitmap()
168 * Return read-only GIRQ result register. Result is bit-wise and of source
179 return regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].RESULT; in mchp_xec_ecia_girq_result()
185 if (nvic_num >= ((SCnSCB->ICTR + 1) * 32)) { in mchp_xec_ecia_nvic_clr_pend()
233 * Clear NVIC pending status given GIRQ source information encoded by macro
234 * MCHP_XEC_ECIA. For aggregated only sources the encoding sets direct NVIC
235 * number equal to aggregated NVIC number.
247 * @param girq is the GIRQ number (8 - 26)
248 * @param src is the interrupt source in the GIRQ (0 - 31)
250 int mchp_xec_ecia_enable(int girq, int src) in mchp_xec_ecia_enable() argument
252 if ((girq < MCHP_FIRST_GIRQ) || (girq > MCHP_LAST_GIRQ) || in mchp_xec_ecia_enable()
254 return -EINVAL; in mchp_xec_ecia_enable()
260 regs->GIRQ[girq - MCHP_FIRST_GIRQ].EN_SET = BIT(src); in mchp_xec_ecia_enable()
269 * @param ecia_info is GIRQ connection encoded with MCHP_XEC_ECIA
273 uint8_t girq = (uint8_t)MCHP_XEC_ECIA_GIRQ(ecia_info); in mchp_xec_ecia_info_enable() local
276 return mchp_xec_ecia_enable(girq, src); in mchp_xec_ecia_info_enable()
282 * @param girq is the GIRQ number (8 - 26)
283 * @param src is the interrupt source in the GIRQ (0 - 31)
285 int mchp_xec_ecia_disable(int girq, int src) in mchp_xec_ecia_disable() argument
287 if ((girq < MCHP_FIRST_GIRQ) || (girq > MCHP_LAST_GIRQ) || in mchp_xec_ecia_disable()
289 return -EINVAL; in mchp_xec_ecia_disable()
295 regs->GIRQ[girq - MCHP_FIRST_GIRQ].EN_CLR = BIT(src); in mchp_xec_ecia_disable()
304 * @param ecia_info is GIRQ connection encoded with MCHP_XEC_ECIA
308 uint8_t girq = (uint8_t)MCHP_XEC_ECIA_GIRQ(ecia_info); in mchp_xec_ecia_info_disable() local
311 return mchp_xec_ecia_disable(girq, src); in mchp_xec_ecia_info_disable()
321 * @param src is the interrupt source in the GIRQ (0 - 31)
329 return -EINVAL; in mchp_xec_ecia_set_callback_by_dev()
335 /* source exists in this GIRQ? */ in mchp_xec_ecia_set_callback_by_dev()
336 if (!(cfg->sources[src] & BIT(7))) { in mchp_xec_ecia_set_callback_by_dev()
337 return -EINVAL; in mchp_xec_ecia_set_callback_by_dev()
341 int idx = (int)(cfg->sources[src] & ~BIT(7)); in mchp_xec_ecia_set_callback_by_dev()
352 * @param girq is the GIRQ number (8 - 26)
353 * @param src is the interrupt source in the GIRQ (0 - 31)
368 * @param ecia_info is GIRQ connection encoded with MCHP_XEC_ECIA
385 * @param src is the interrupt source in the GIRQ (0 - 31)
390 return -EINVAL; in mchp_ecia_unset_callback_by_dev()
396 /* source exists in this GIRQ? */ in mchp_ecia_unset_callback_by_dev()
397 if (!(cfg->sources[src] & BIT(7))) { in mchp_ecia_unset_callback_by_dev()
398 return -EINVAL; in mchp_ecia_unset_callback_by_dev()
402 int idx = (int)(cfg->sources[src] & ~BIT(7)); in mchp_ecia_unset_callback_by_dev()
413 * @param girq is the GIRQ number (8 - 26)
414 * @param src is the interrupt source in the GIRQ (0 - 31)
426 * @param ecia_info is GIRQ connection encoded with MCHP_XEC_ECIA
438 * Create a build time flag to know if any aggregated GIRQ has been enabled.
439 * We make use of DT FOREACH macro to check GIRQ node status.
440 * Enabling a GIRQ node (status = "okay") implies you want it used in
441 * aggregated mode. Note, GIRQ 8-12, 24-26 are aggregated only by HW design.
442 * If a GIRQ node is disabled(status = "disabled") and is direct capable the
444 * functions in this driver to set/clear GIRQ enable bits and status.
446 * aggregation by managing the GIRQ itself.
459 * Generic ISR for aggregated GIRQ's.
460 * GIRQ source(status) bits are latched (R/W1C). The peripheral status
461 * connected to the GIRQ source bit must be cleared first by the callback
462 * and this routine will clear the GIRQ source bit. If a callback was not
465 * NOTE: dev_girq is a pointer to a GIRQ child device instance.
471 struct girq_regs *girq = (struct girq_regs *)cfg->base; in xec_girq_isr() local
472 int girq_id = GIRQ_ID_TO_BITPOS(cfg->girq_id); in xec_girq_isr()
474 uint32_t result = girq->RESULT; in xec_girq_isr()
477 uint8_t bitpos = 31 - (__builtin_clz(result) & 0x1f); in xec_girq_isr()
479 /* clear GIRQ latched status */ in xec_girq_isr()
480 girq->SRC = BIT(bitpos); in xec_girq_isr()
484 if (cfg->sources[bitpos] & BIT(7)) { in xec_girq_isr()
486 idx = (uint32_t)cfg->sources[bitpos] & ~BIT(7); in xec_girq_isr()
491 girq->EN_CLR = BIT(bitpos); in xec_girq_isr()
494 girq->EN_CLR = BIT(bitpos); in xec_girq_isr()
504 * the data transfer is complete the system re-enters deep sleep unless the
506 * GIRQ22 aggregated output and sources are not connected to the NVIC.
507 * We enable GIRQ22 aggregated output to ensure clock asynchronous wake
513 (const struct xec_ecia_config *const) (dev->config); in xec_ecia_init()
516 struct ecia_regs *const ecia = (struct ecia_regs *)cfg->ecia_base; in xec_ecia_init()
521 return -ENODEV; in xec_ecia_init()
525 (clock_control_subsys_t)&cfg->clk_ctrl); in xec_ecia_init()
531 ecs->INTR_CTRL |= BIT(0); in xec_ecia_init()
533 /* gate off all aggregated outputs */ in xec_ecia_init()
534 ecia->BLK_EN_CLR = UINT32_MAX; in xec_ecia_init()
536 /* connect aggregated only GIRQs to NVIC */ in xec_ecia_init()
537 ecia->BLK_EN_SET = MCHP_ECIA_AGGR_BITMAP; in xec_ecia_init()
541 ecia->GIRQ[n].EN_CLR = UINT32_MAX; in xec_ecia_init()
545 nr = SCnSCB->ICTR; in xec_ecia_init()
547 NVIC->ICER[n] = UINT32_MAX; in xec_ecia_init()
548 NVIC->ICPR[n] = UINT32_MAX; in xec_ecia_init()
551 /* ecia->BLK_ACTIVE = xec_chk_req; */ in xec_ecia_init()
556 /* xec_config_girq_xxx.sources[] entries from GIRQ node */
561 /* Parameter n is a child node-id */
601 /* n = GIRQ node id */
618 /* look up GIRQ node handle from ECIA configuration */
626 girq_num -= MCHP_FIRST_GIRQ; in get_girq_dev()