1 /* 2 * Copyright (c) 2019 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <zephyr/device.h> 8 #include <zephyr/init.h> 9 #include <soc.h> 10 #include <zephyr/drivers/pinctrl.h> 11 #include <zephyr/kernel.h> 12 #include <zephyr/arch/cpu.h> 13 #include <cmsis_core.h> 14 15 /* 16 * Initialize MEC1501 EC Interrupt Aggregator (ECIA) and external NVIC 17 * inputs. 18 */ soc_ecia_init(void)19static int soc_ecia_init(void) 20 { 21 GIRQ_Type *pg; 22 uint32_t n; 23 24 mchp_pcr_periph_slp_ctrl(PCR_ECIA, MCHP_PCR_SLEEP_DIS); 25 26 ECS_REGS->INTR_CTRL |= MCHP_ECS_ICTRL_DIRECT_EN; 27 28 /* gate off all aggregated outputs */ 29 ECIA_REGS->BLK_EN_CLR = 0xFFFFFFFFul; 30 /* gate on GIRQ's that are aggregated only */ 31 ECIA_REGS->BLK_EN_SET = MCHP_ECIA_AGGR_BITMAP; 32 33 /* Clear all GIRQn source enables and source status */ 34 pg = &ECIA_REGS->GIRQ08; 35 for (n = MCHP_FIRST_GIRQ; n <= MCHP_LAST_GIRQ; n++) { 36 pg->EN_CLR = 0xFFFFFFFFul; 37 pg->SRC = 0xFFFFFFFFul; 38 pg++; 39 } 40 41 /* Clear all external NVIC enables and pending status */ 42 for (n = 0u; n < MCHP_NUM_NVIC_REGS; n++) { 43 NVIC->ICER[n] = 0xFFFFFFFFul; 44 NVIC->ICPR[n] = 0xFFFFFFFFul; 45 } 46 47 return 0; 48 } 49 configure_debug_interface(void)50static void configure_debug_interface(void) 51 { 52 /* No debug support */ 53 ECS_REGS->DEBUG_CTRL = 0; 54 ECS_REGS->ETM_CTRL = 0; 55 56 #ifdef CONFIG_SOC_MEC1501_DEBUG_WITHOUT_TRACING 57 /* Release JTAG TDI and JTAG TDO pins so they can be 58 * controlled by their respective PCR register (UART2). 59 * For more details see table 44-1 60 */ 61 ECS_REGS->DEBUG_CTRL = (MCHP_ECS_DCTRL_DBG_EN | 62 MCHP_ECS_DCTRL_MODE_SWD); 63 #elif defined(CONFIG_SOC_MEC1501_DEBUG_AND_TRACING) 64 #if defined(CONFIG_SOC_MEC1501_DEBUG_AND_ETM_TRACING) 65 #pragma error "TRACE DATA are not exposed in HW connector" 66 #elif defined(CONFIG_SOC_MEC1501_DEBUG_AND_SWV_TRACING) 67 ECS_REGS->DEBUG_CTRL = (MCHP_ECS_DCTRL_DBG_EN | 68 MCHP_ECS_DCTRL_MODE_SWD_SWV); 69 #endif /* CONFIG_SOC_MEC1501_DEBUG_AND_TRACING */ 70 71 #endif /* CONFIG_SOC_MEC1501_DEBUG_WITHOUT_TRACING */ 72 } 73 soc_early_init_hook(void)74void soc_early_init_hook(void) 75 { 76 uint32_t isave; 77 78 79 isave = __get_PRIMASK(); 80 __disable_irq(); 81 82 soc_ecia_init(); 83 84 /* Configure GPIO bank before usage 85 * VTR1 is not configurable 86 * VTR2 doesn't need configuration if setting VTR2_STRAP 87 */ 88 #ifdef CONFIG_SOC_MEC1501_VTR3_1_8V 89 ECS_REGS->GPIO_BANK_PWR |= MCHP_ECS_VTR3_LVL_18; 90 #endif 91 92 configure_debug_interface(); 93 94 if (!isave) { 95 __enable_irq(); 96 } 97 } 98
