Searched full:plli2s (Results 1 – 18 of 18) sorted by relevance
| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32f411-plli2s-clock.yaml | 11 f(PLLI2S_R) = f(VCO clock) / PLLI2S R --> PLLI2S
13 with f(VCO clock) = f(PLL I2S clock input) × (PLLI2S N / PLLI2S M)
16 compatible: "st,stm32f411-plli2s-clock"
18 include: st,stm32f4-plli2s-clock.yaml
31 PLLI2S division factor for I2S Clocks to supply USB/SDIO/RNG
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| D | st,stm32f4-plli2s-clock.yaml | 11 f(PLL_R) = f(VCO clock) / PLLR --> PLLI2S
16 compatible: "st,stm32f4-plli2s-clock"
28 PLLI2S multiplication factor for VCO
35 PLLI2S division factor for I2S Clocks
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| /Zephyr-latest/dts/arm/st/f4/ |
| D | stm32f411.dtsi | 11 plli2s: plli2s { label
13 compatible = "st,stm32f411-plli2s-clock";
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| D | stm32f401.dtsi | 11 plli2s: plli2s { label
13 compatible = "st,stm32f4-plli2s-clock";
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| D | stm32f446.dtsi | 13 plli2s: plli2s { label
14 compatible = "st,stm32f411-plli2s-clock";
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| D | stm32f412.dtsi | 14 plli2s: plli2s { label
16 compatible = "st,stm32f411-plli2s-clock";
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| /Zephyr-latest/samples/boards/st/mco/boards/ |
| D | nucleo_f446ze.overlay | 1 /* Enable the PLLI2s and set it as clock source for the MCO2 (with prescaler 2) : 25MHz */
3 &plli2s {
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| D | nucleo_f411re.overlay | 1 /* Enable the PLLI2s and set it as clock source for the MCO2 (with prescaler 5) */
3 &plli2s {
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| /Zephyr-latest/boards/shields/x_nucleo_iks02a1/boards/ |
| D | nucleo_f411re.overlay | 7 &plli2s {
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| /Zephyr-latest/include/zephyr/drivers/clock_control/ |
| D | stm32_clock_control.h | 175 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f4_plli2s_clock, okay)
178 #define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n)
179 #define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r)
180 #define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
183 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f412_plli2s_clock, okay)
185 #define STM32_PLLI2S_M_DIVISOR DT_PROP(DT_NODELABEL(plli2s), div_m)
186 #define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n)
187 #define STM32_PLLI2S_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_q)
188 #define STM32_PLLI2S_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_q, 1)
189 #define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r)
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/ |
| D | f4_sdmmc48_pll.overlay | 15 &plli2s {
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| D | f4_i2s2_pll.overlay | 66 &plli2s {
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/ |
| D | test_stm32_clock_configuration_i2s.c | 49 "Expected I2S src: PLLI2S (0x%lx). Actual I2S src: 0x%x", in ZTEST()
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| D | test_stm32_clock_configuration_sdmmc.c | 80 /* Get the CK48M source : PLL Q or PLLI2S Q */ in ZTEST()
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_stm32f2_f4_f7.c | 161 /* There is a Q divider on the PLLI2S to configure the PLL48CK */ in config_plli2s()
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| /Zephyr-latest/boards/96boards/argonkey/ |
| D | 96b_argonkey.dts | 70 &plli2s {
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| /Zephyr-latest/boards/96boards/stm32_sensor_mez/ |
| D | 96b_stm32_sensor_mez.dts | 74 &plli2s {
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| /Zephyr-latest/doc/releases/ |
| D | release-notes-3.3.rst | 3009 * :github:`53808` - Improve PLLI2S VCO precision
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